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C68000 Microprocessor

IP Vendor: 
CAST, Inc.
IP Target Vendor: 
Altera
IP Type: 
Design
IP Category: 
Embedded Processing
IP Supported FPGA Device: 
Apex 20KC
Apex 20KE
Apex II
Cyclone
Flex 10KE
Stratix
Stratix II
IP Description: 

"Features
Encrypts and decrypts using the AES Rijndael Block Cipher Algorithm
Satisfies Federal Information Processing Standard (FIPS) Publication 197 from the US National Institute of Standards and Technology (NIST)
Processes 128-bit data in 32-bit blocks
Employs user-programmable key size of 128, 192, or 256 bits
Smallest version supports a single block cipher mode, Electronic Codebook (ECB); these modes can be added as needed: Cipher Block Chaining (CBC), Cipher Feedback (CFB), Output Feedback (OFB), Counter (CTR), and Counter with CBC-MAC (CCM)
Works with a pre-expanded key or can integrate the optional key expansion function
Simple, fully synchronous, reusable design
Available as fully functional and synthesizable VHDL or Verilog HDL, or as a netlist for popular programmable devices
Complete deliverables include test benches
Block Diagram

Description
The AES megafunction implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit blocks, and is programmable for 128-, 192-, and 256-bit key lengths.

Different versions provide the best speed/area results for specific applications. Various cipher modes can be supported (ECB, CBC, OFB, CFB, CTR, CCM), different datapath widths are possible, and smaller or faster architectures are available. The megafunction works with a pre-expanded key, or with optional key expansion logic.

The fully synchronous design is available optimized for a variety of Altera devices."

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