Home
World's Largest FPGA/CPLD Portal


Poll

What is your preferred platform for FPGA Design Flow ?
Windows
54%
Linux
37%
Solaris
1%
Mixed
3%
Other
1%
No preference
4%
Total votes: 3278

Block Viterbi Decoder

IP Vendor: 
Lattice
IP Target Vendor: 
Lattice
IP Type: 
Design
IP Category: 
Bus Interface and IO
IP Description: 

"Features
Compatible with the following standards: IEEE 802.16-2004 SC PHY/ OFDM PHY, IEEEE802.11a, 3GPP, 3GPP2, and DVB-S
Supports multiple code rates: 1/2, 1/3, ... 1/7 for non-punctured codes, 2/3, 3/4, ..., 12/13 for punctured codes, and from m/(m+1) to m/(2m-1), where m is from 1 to 12, for dynamic punctured codes
Variable constraint length from 3 to 9
Supports dynamically variable code rates and puncture patterns
Dynamic BER estimation option
One-clock synchronous design
Hard or parameterizable soft decision decoding. Hard and soft decision for non-punctured codes and soft decision for punctured codes
Fully parallel or hybrid implementations. For a hybrid implementation, the degree of parallelism is parameterizable
Parameterizable trace-back length
Signed and unsigned representations for soft decision data
Supports parameterized puncturing patterns
Supports both continuous and block data input
Supports both Tail Biting and Zero Flushing block convolutional codes
Supports both one and two traceback schemes to cater to different coding scenarios"

Facebook  Twitter  Linkedin  Orkut  YouTube      RSS

Check out FPGA related videos

Find Us On Facebook