Poll

What is your preferred platform for FPGA Design Flow ?:

G.975.1 A4 Enhanced Forward Error Correction (EFEC)

IP Type: 
Design
IP Description: 

Compliant to the G.975.1.4 standard, this optical transport FEC can acheive high gain for 10G and 40G applications that can help replace ASSPs

Compliant to the G.975.1.4 standard, this optical transport FEC can acheive high gain for 10G and 40G applications that can help replace ASSPs

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