Poll

What is your preferred platform for FPGA Design Flow ?:

2.5G STS-48/STM-16 Framer, Pointer Processer and POS Mapper

IP Type: 
Design
IP Description: 

Combining framer, overhead processor, pointer processor, and data link logic into a single flexible FPGA, the Crowsnest allows for cost-effective deployment of 2.5 Gbps systems.

Combining framer, overhead processor, pointer processor, and data link logic into a single flexible FPGA, the Crowsnest allows for cost-effective deployment of 2.5 Gbps systems.

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