World's Largest FPGA/CPLD Portal
Poll
What is your preferred platform for FPGA Design Flow ?
Windows
54%
Linux
37%
Solaris
1%
Mixed
3%
Other
1%
No preference
4%
Total votes: 3278
2.5G STS-48/STM-16 Framer, Pointer Processer and POS Mapper
IP Vendor:
Avalon Microelectronics, Inc.
IP Type:
Design IP Description:
Combining framer, overhead processor, pointer processor, and data link logic into a single flexible FPGA, the Crowsnest allows for cost-effective deployment of 2.5 Gbps systems.
Combining framer, overhead processor, pointer processor, and data link logic into a single flexible FPGA, the Crowsnest allows for cost-effective deployment of 2.5 Gbps systems.
Check out FPGA related videos
Find Us On Facebook
FPGA Central is a website bringing the FPGA (Field Programable Gate Array), CPLD , PLD, VLSI community together at one central location. Some Keywords: FGPA, FPGA, EDA Tools, FPGA Design, Central, Programmable logic, LUT, VLSI, SoC, Journal
Privacy Policy || Terms of Use
 |
 |