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H>264 CODEC for FPGAs

IP Vendor: 
A2E Technologies, LLC
IP Target Vendor: 
Xilinx
IP Code Language: 
System Verilog
IP Type: 
Design
IP Category: 
Audio, Video and Image Processing
IP Description: 

Our FPGA core is highly optimized and 80% SMALLER THAN THE COMPETITION! It is capable of being synthesized in Xilinx FPGAs and supports H.264 variable and fixed bit-rate encoding of video streams. Encodes video data at 1.5 clocks/pixel. Typical clock rate in an Xilinx SPARTAN 6 is 70Mhz. Typical clock rate in a Xilinx Virtex 6 is 140MHz. Multiple cores can be used for processing larger size or higher bandwidth images. Uses FPGA specific DDR 3 controller and microprocessor soft core. Built in Decoder that can decode A2e H.264 encoded streams. In addition, the standard core can be customized, retaining ITAR compliance, to meet unique functional needs.

In addition, the standard core can be customized, retaining ITAR compliance, to meet unique functional needs..

- Designed for high-speed, high-pixel count CMOS sensors interfacing to medium to high-bandwidth connections
- 1.5 clocks/pixel processing rate
- Built in H.264 Decoder that can decode A2e specific H.264 encoded streams
- Fully compatible with the ITU-T H.264 specification
- Supports resolutions up to 4096 x 4096 (can be expanded with additional cores)
- Supports simultaneous encoding of multiple streams of arbitrary sizes and compression ratios
- Generates I and P frames
- Variable Bit Rate (VBR) and Constant Bit Rate (CBR)
- Search range: 80 X 48 pixels, Full, 1/2, 1/4 pixel resolution
- Entropy Encoding: CAVLC
- Support for intra 4 x 4 DC prediction
- Support for Single or Multiple slices via firmware control
- Supports YUV 4:2:0 video input
- Fully synchronous design
- Available as FPGA specific netlist
- Custom versions available

Additional Functional Options
- I Frame Only
- Variable Bit Depth
- Xilinx AXI Bus Support

Deliverables
-FPGA specific netlist
-Bit accurate C model
-Complete HDL testbench
-Test images (x,y,z)
-Complete data sheet
-Download the Data Sheet!

See our Data Sheet download link in the right column or click here: Download Data Sheet. The Data Sheet contains more details on functionality and deliverables. Or, you can contact the sales person in your area to learn more. ([email protected], or numbers at the bottom of this page)

Pricing

Please contact us at [email protected] for pricing information and any other questions.

The new H.264-15 core represents a huge leap in performance with just a small increase in size over our old standard core. Encoding and decoding performance has been doubled with just a 25% increase in gate count. A single H.264-15 core is capable of compressing 1080p30 video in a single Spartan device. Additionally, we’ve added a more flexible bus interface that allows simultaneous and asynchronous ac-cess to reference frame memory, video input data, and compressed data (in or out). Support for the latest Xilinx devices such as Zynq and Kintex has also been added. A complete IP camera can now be created in a single, low-cost Zynq device!

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