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USB 3.0 Host Controller

IP Vendor: 
PLDA
IP Target Vendor: 
Altera
IP Code Language: 
Verilog
IP Code Language: 
VHDL
IP Type: 
Design
IP Supported FPGA Device: 
Cyclone III
Stratix
Stratix GX
IP Description: 
  • USB 3.0 Host IP core in synthezisable Verilog RTL (encrypted or source code)
    • Includes Physical, Link, and Protocol layers
    • Includes xHCI Host Controller
    • Complies to the USB 3.0 Specification, revision 1.0
    • Full support for legacy USB 2.0
      • With PLDA USB 2.0 Core Layer
      • Or with 3rd-party USB 2.0 IP through intelligent multiplexing
    • Core frequency: 125 Mhz
    • Available user interfaces include AMBA 2 AHB or AMBA 3 AXI
    • Asynchronous clocking between Core and user interface logic (CDC)
    • Configurable buffer sizes
    • USB 3.0 PIPE interface to PHY (8-,16-, or 32-bit)
    • Full Power Management support (U1,U2,U3)
      • LFPS support
      • Support Isochronous and Bulk Stream traffic
  • USB 3.0 Host IP simulation models
  • USB 3.0 Testbench simulation libraries
  • PIPE wrappers and Physical Coding Sub-layers (PCS)
    • For the supported Altera FPGA devices with embedded PCI Express® 5.0 Gbit transceivers
    • For the supported external USB 3.0 PHY chips
  • Configuration assistant GUI (Wizard)
    • Multi-platform JAVA based

PLDA USB 3.0 Host Controller is a high performance, low gate count semiconductor IP that adds SuperSpeed USB Host connectivity to Altera FPGAs. The controller is compliant to the Intel xHCI specification and implements all of the digital layers defined by the USB 3.0 Specification while providing full backward compatibility to USB 2.0. PHY interface options include FPGA embedded 5.0 Gbit transceivers as well as discrete USB 3.0 PHY chips. User interface options include AMBA 2 AHB and AMBA 3 AXI.

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