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8B10B Encoder/Decoder

IP Vendor: 
Altera
IP Target Vendor: 
Altera
IP Type: 
Design
IP Category: 
Communication and Networking
IP Supported FPGA Device: 
Cyclone
Cyclone II
Cyclone III
Hardcopy II
Hardcopy Stratix
Stratix
Stratix GX
Stratix II
Stratix II GX
Stratix III
IP Description: 

"Features
8b/10b encoding and decoding
Cascaded encoding and decoding
Industry compatible special character coding
Easy-to-use MegaWizard® interface
IP functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators
Complies with all applicable standards, including:
Institute of Electrical and Electronics Engineers, IEEE 802.3z, Media Access Control (MAC) Parameters, Physical Layer, Repeater and Management Parameters for 1000 Mb/s Operation, 1998, paragraphs 36.2.4.1 to 36.2.4.6
American National Standards Institute, ANSI X3.230, Fibre Channel Physical and Signaling Interface (FC-PH ), 1994
International Telecommunication Union, ITU-T Recommendation G.7041, Generic Framing Procedure, October 2001
General Description
Encoders and decoders are used for physical layer coding for Gigabit Ethernet, Fibre Channel, and other applications. The 8b/10b encoder takes byte inputs, and generates a direct current (DC) balanced stream (equal number of 1s and 0s) with a maximum run length of 5. Some of the individual 10-bit codes will have an equal number of 1s and 0s, while others will have either four 1s and six 0s, or, six 1s and four 0s. In the latter case, the disparity between 1s and 0s is used as an input to the next 10-bit code generation, so that the disparity can be reversed, and maintain an overall balanced stream. For this reason, some 8-bit inputs have two valid 10-bit codes, depending on the input disparity.

The Altera® 8B10B Encoder/Decoder is a compact, high performance MegaCore® function capable of encoding and decoding in multi-gigabit applications."

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