8b/10b Encoder/Decoder

Many serial data transmission standards utilize 8b/10b encoding to ensure sufficient data transitions for clock recovery. This reference design describes an encoder/decoder suitable for performing 8b/10b encoding/decoding within Lattice programmable logic devices (PLDs). This encoding/decoding logic can be combined with the high-speed serial interface blocks (sysHSI blocks) contained in the ispXPGA and ispGDX2 devices to support high speed interfaces that utilize this encoding scheme. Two CPLD implementations for the ispGDX2 device family along with the ispXPGA implementation are provided for use with sysHSI blocks.