World's Largest FPGA/CPLD Portal
Poll
What is your preferred platform for FPGA Design Flow ?
Windows
54%
Linux
37%
Solaris
1%
Mixed
3%
Other
1%
No preference
4%
Total votes: 3278
8254 Programmable Interval Timer/Counter
IP Vendor:
eInfochips Ltd.
IP Target Vendor:
Xilinx
IP Type:
Design
IP Category:
Embedded Processing IP Supported FPGA Device:
Virtex-II
IP Description:
"The eInfochips e8254 core is a counter/timer device designed to solve the common timing control problems in microcomputer system design. It provides three independent 16-bit counters, each counter may operate in different modes. All modes are software progammable using a CPU.
Device Family Support
Virtex-II
Spartan
Key Features
Status register
Six programmable counter modes
Intel 8254 like"
Check out FPGA related videos
Find Us On Facebook
FPGA Central is a website bringing the FPGA (Field Programable Gate Array), CPLD , PLD, VLSI community together at one central location. Some Keywords: FGPA, FPGA, EDA Tools, FPGA Design, Central, Programmable logic, LUT, VLSI, SoC, Journal
Privacy Policy || Terms of Use
 |
 |