User login

32-Bit PCI Bus Master/Target Interface

IP Type:
Design
IP Target Vendor:
Altera
IP Category:
Bus Interface and IO
IP Supported FPGA Device :
Apex 20KC
Apex 20KE
Cyclone II
Excalibur
Flex 10KE
Stratix
Stratix II
IP Description:

"Features
Fully compliant with peripheral component interconnect (PCI) special interest group (SIG) PCI Local Bus Specification, Revision 2.2
Supports zero-wait state burst data transfer
Provides bus initiator and target capability
33-MHz operating frequency

Description
The 32-bit PCI master/target interface megafunction is a flexible interface between a bus master device, such as a direct-memory access (DMA) controller or video coprocessor, and the PCI bus. The megafunction supports high bandwidth data transfer up to 133 Mbytes per second. All PCI configuration registers are included in the megafunction, and configuration requests are processed locally by the megafunction.

This megafunction also includes PCI target capability, which is useful for transferring data as a target and for setting up the control register of a bus mastering device.

The megafunction is available in Altera Hardware Description Language (AHDL), Verilog HDL, VHDL, and netlist format."

Average rating
(1 vote)

Upcoming FPGA Events