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32/64-Bit PCI Bus Target Interface, 33/66 MHz

IP Vendor: 
IP Target Vendor: 
IP Type: 
IP Category: 
Bus Interface and IO
IP Supported FPGA Device: 
Apex 20KC
Apex 20KE
Cyclone II
Flex 10KE
IP Description: 

Compliant with the Peripheral Component Interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2
Compliant with the Personal Computer Memory Card International (PCMCIA) CardBus PC Card Standard, Release 8
Supports Power Management Specification, Revision 1.1 for all power states
Supports CIS register and CIS tupple space
Supports function event registers
Supports clock management (CLKRUN#)
Compliant with the PICMG CompactPCI Specification, Revision 2.1
Compliant with the PICMG Hot Swap Specification, Revision 1.0
Compliant with the PCI SIG PCI Local Bus Mini PCI Specification, Revision 1.0
Additional standards supported include PMC (MMSC PMC Specification, Draft 2.4) and PC104+ (PC/104 PC/104+ Specification, Revision 1.0)
Optimized for Altera® FLEX® 10KE, ACEX™ 1K, APEX™ 20K, APEX 20KE, APEX 20KC, APEX II, and ARM®- and MIPS-based™ Excalibur™ devices
66-MHz PCI-compliant with FLEX 10KE, ACEX 1K, APEX 20KE, and Excalibur devices in -1 speed grade, and with all APEX II devices
Operating frequency of over 100 MHz on specific Altera devices for utilization in embedded systems
VHDL-RTL source code available (with application-specific integrated circuit (ASIC) licenses only)
Silicon-proven core with over 300 licensees worldwide, including ASIC licensees
Risk-free OpenCore® evaluation available
Target-mode advanced features include:
True multifunction support for up to 4 functions, with up to 4 interrupt lines
Supports all base address registers (BARs) in both 32-bit and 64-bit addressing modes
Embedded memory controller for each implemented BAR allows for direct memory interfacing (SRAM, DPRAM, and first-in first-out (FIFO))
Configuration space can be mapped into memory space
For additional features, refer to the PCI MegaCore Function User Guide
Master-mode advanced features include:
Up to four embedded direct memory access (DMA) channels, independently operated
Complete support of memory write and invalidate (MWI) command for DMA-transfer optimization
64-bit addressing and 64-bit data transfers supported and dynamically negotiated
For additional features, refer to the PCI MegaCore Function User Guide
Ready for PCI host-bridge implementations when used in conjunction with PLD Applications' PCI arbiter core"

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