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"The D16750 is a soft Core of a Universal Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C750. The D16750 allows serial transmission in two modes: UART mode and FIFO mode. In FIFO mode internal FIFOs are activated allowing 64 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit directions. D16750 performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions. D16750 includes a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to (216-1), and producing a 16 × clock for driving the internal transmitter logic. Provisions are also included to use this 16 × clock to drive the receiver logic. The D16750 has complete MODEM control capability, and a processor-interrupt system. In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software overload and increase system efficiency by automatically controlling serial data flow through input signals (RTS,CTS).

Device Family Support

Virtex-4 FX

Virtex-4 LX

Virtex-4 SX

Virtex-II Pro

Spartan-3L

Spartan-3E

Spartan-3

Spartan-IIE

Key Features

Software compatible with 16450, 16550 and 16750 UARTs

Configuration capability

Separate configurable BAUD clock line

Full prioritized interrupt system controls, with independently controlled transmit, receive, line status and data set interrupts

In the FIFO mode receiver and transmitter are each buffered with 16 or 64 byte FIFO to reduce the number of interrupts presented to the CPU. There is optional FIFO size extention to 128, 256 or 512 Bytes. The D16750 has also DMA Modes, allows single and multitransfer

Fully programable serial-interface characteristics, 16 bit programmable baud generator

Fully synthesizable static design with no internal tri-state buffers, technology independent HDL Source Code"