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What is your preferred platform for FPGA Design Flow ?:

10 Gigabit Fibre Channel FC-1 Core

IP Vendor: 
MorethanIP GmbH
IP Target Vendor: 
Altera
IP Type: 
Design
IP Category: 
Communication and Networking
IP Supported FPGA Device: 
Stratix
Stratix II
IP Description: 

"Features
Complies with the American National Standards Institute (ANSI) T11 10-GFC (Gigabit Fibre Channel) Rev. 3.0 specification
Includes optional media-independent 64-bit, non-double data rate (DDR) interface or standard 32-bit, 10-Gbit medium independent interface (XGMII) DDR interface to connect to FC-2 and higher layers
Includes optional 10-Gbit attachment unit interface (XAUI) interface implemented with embedded quad serializer/deserializer (SERDES), which provides an efficient board-level interface to optical modules and loopback
Implements 4-to-1, 10-Gbit 16-bit interface (XSBI) multiplexer/de-multiplexer when selected technology is Altera® CPLD to connect to FC-0 physical layers
Implements a 10-GFC data scrambler which generates transition-rich signals to the application high-speed optical link and data descrambler on the core receive path
Features a 64- and 66-bit data coder/decoder (CODEC) with synchronization header insertion or deletion on respective transmit or receive
Performs 66-bit block synchronization on the PCS receive path and 66-bit block encoding on transmit with gearbox function
Includes 64- to 66-bit encoder-decoder performing 66-bit word alignment, the 64- to 66-bit receive path decoding, the 64- or 66-bit transmit path encoding, and the 64- to 66-bit transmit path conversion for block overhead bits
Implements XGMII-XSBI clock rate decoupling with elastic buffers on the transmit and receive paths
Provides rate-matching first-in first-out (FIFO) with idle insertion-and-removal in receive direction, simplifying system clock distribution
Performs programmable loopback on the core XGMII interface available for application test
Implements test pattern generator-checker for link testing and in-system testing
Implements bit error rate monitoring, with high error rate indication, which provides constant line-quality monitoring
Helps to reduce time-to-market and provide cost-effective solutions for Altera Stratixâ„¢ CPLDs or ASIC implementations
Contains complete design kit which includes frame generators and checking models, standard compliance scenario and implementation scripts for various ASICs, and programmable logic technologies"

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