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10 Gigabit Ethernet Physical Coding Sublayer (PCS)

May 29, 2007 - 11:34pm — fc
IP Vendor: 
MorethanIP GmbH
IP Target Vendor: 
Altera
IP Type: 
Design
IP Category: 
Communication and Networking
IP Supported FPGA Device: 
Cyclone
Cyclone II
Stratix
Stratix GX
Stratix II
Stratix II GX
IP Description: 

"Features
10-GBASE-R core is compliant with Clause 49 of IEEE 802.3ae specification
Designed for 10-Gbit Ethernet physical layer (PHY) applications such as local area network/wide area network (LAN/WAN) PHYs or for use in integrated 10-Gbit Ethernet controller devices
Optional features include 64-bit, media-independent non-double data rate (DDR) interface; 32-bit XGMII (10-Gbit medium independent interface) DDR-to-10-Gbit Ethernet media access controls (MACs); and high-speed serializer/deserializer (SERDES)
Optional 10-Gbit attachment unit interface (XAUI) can be implemented with transceivers for efficient, board-level interface to optical modules and loopback
Optional XAUI interface is compatible with the Xenpack version 2.0 specification
Implements 4-to-1, 10-Gbit 16-bit interface (XSBI) multiplexer/de-multiplexer when selected technology is an Altera® FPGA
Implements 10-Gbit Ethernet data scrambler that generates transition-rich signals to an application's high-speed optical link and its data descrambler on the core receive path
Available for Altera's Stratixâ„¢ and Stratix GX FPGAs
Includes 64- and 66-bit data coder/decoder (CODEC), with synchronization bit insertion or deletion upon respective transmit or receive
Provides 66-bit block synchronization on the physical coding sub-layer receive path, and 64-bit block encoding on transmit with gearbox function
Includes 64- and 66-bit encoder/decoder that performs 66-bit word alignment; 64- and 66-bit receive path decoding; 64- and 66-bit transmit path encoding; and 64- and 66-bit transmit path conversion for block overhead bits
Implements XGMII and XSBI clock rates decoupling with elastic buffers on the transmit and receive paths
Simplifies system clock distribution through rate-matching first-in first-out (FIFO) with idle insertion or removal in receive direction
Provides programmable loopback on the core XGMII interface available for application test
Implements test pattern generator and checker for link testing in accordance with Clauses 49.2.8 and 49.2.12 of IEEE 802.3ae
Implements bit error rate monitoring, with high error rate indication to ensure constant line quality monitoring
Connects seamlessly to the MorethanIP 10-Gbit Ethernet MAC to function as a single-chip 10-Gbit Ethernet controller
Optional Management Data Interface (xMDIO) provides access to the internal registers of the PCS according to Clause 45 (definition of extended MDIO) of IEEE 802.3ae
Includes complete design kit containing behavioral Ethernet frame generators and checking models, PCS traffic generation model, standard compliance scenario, and implementation scripts"