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10 Gigabit Ethernet Media Access Controller

IP Vendor: 
Xilinx
IP Target Vendor: 
Xilinx
IP Type: 
Design
IP Category: 
Communication and Networking
IP Supported FPGA Device: 
Virtex-5 LXT
IP Description: 

"Xilinx provides a parameterizable LogiCOREâ„¢ solution for the 10 Gigabit per second (Gbps) Ethernet Media Access Controller function used to interface to Physical Layer devices in a 10Gbps Ethernet (10GE) system. The core is designed to work with the latest Virtexâ„¢-5, Virtex-4, Virtex-II Pro, and Virtex-II platform FPGAs and integrate seamlessly into the Xilinx design flow.
The 10GEMAC core is designed to the IEEE 802.3ae-2002 specification and supports the high-bandwidth demands of network Internet Protocol (IP) traffic on LAN, MAN and WAN networks.

The Xilinx 10Gb Ethernet MAC core is another of the SystemIO solutions which provide high-performance interconnect technologies for communications equipment and flexibility in implementing emerging interface standards. The MAC core performs the Link function of the 10Gb Ethernet standard. The 10 Gigabit Media Independent Interface (XGMII) version of this core is intended to interface to either an off-chip PHY device or XAUI LogiCORE using the XGMII Interface.

Device Family Support

Virtex-5 LXT

Virtex-5 LX

Virtex-4 FX

Virtex-4 LX

Virtex-4 SX

Virtex-II Pro

Virtex-II

Key Features

Designed to IEEE 802.3ae-2002 specification

Configured and monitored through an independent microprocessor-neutral interface

Optional Statistics counters

Configurable flow control through MAC Control pause frames; symmetrically or asymmetrically enabled

Generate customized core using the CORE Generator

Cut-through operation with minimum bufferingfor maximum flexibility in 64-bit client bus interfacing

Ability to generate core with no physical interface to allow users to connect the PHY-side interface of the core to user logic

Powerful EtherStats-based statistics gathering

Programmable Interframe Gap

Custom preamble preservation mode

Supports Deficit Idle Control (DIC) for max. data throughput

Maintains minimum IFG under all conditions and line rate performance

Remote Fault/Local Fault signaling at the Reconciliation Sublayer"

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