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"Features
Full media access control (MAC) layer and reconciliation sub-layer implementation compliant with the IEEE 802.3ae specification
Dynamically configurable for network interface card (NIC) and switching or bridging between applications
Optional direct interface to standard 32-bit double data rate (DDR) 10-Gbit medium independent interface (XGMII) connections, or to a selection of high-speed serializer/deserializer (SERDES) devices via a 32-bit SSTL-2 or a high-speed transceiver logic (HSTL) Class I interface
Optional 10-Gbit attachment unit interface (XAUI) implemented with an embedded transceiver that provides an efficient board level interface to optical modules and loopback
Optional XAUI interface compatible with Xenpack version 2.0 specification
Lane and data alignment, physical layer (PHY) error, and local/remote fault signaling handled by the core's reconciliation sub-layer
Cyclic redundancy code (CRC)-32 checking at full speed, using a multi-stage CRC calculation architecture with optional forwarding of the frame check sequence (FCS) field to the user application
CRC-32 generate and append on transmittal or forwarding of user application-provided FCS (selectable on a per-frame basis)
Optional MAC address comparison-on-receive and overwrite-on-transmit for NIC applications
Selectable promiscuous frame receive mode and transparent MAC address forwarding on transmit
Optional multicast address filtering, with 64-bit hash code look-up table (LUT) on receive to reduce processing load on higher layers
Automatic discard of badly received frames, such as frames with preamble or length errors
Optional Ethernet pause frame (IEEE 802.3, Annex 31A) termination, providing fully automated flow control without user application overhead
Optional forwarding of received pause frames to the user application
Optional automatic pause frame generation from programmable first-in first-out (FIFO) congestion thresholds, or by dedicated command pin with programmable quanta
Programmable frame maximum length providing support for any frame, including Jumbo Frame or any tagged frame
Support for VLAN-tagged frames (in accordance with IEEE 802.1Q) in both transmit and receive
Dynamic inter packet gap (IPG) calculation for wide area network (WAN) applications
Deficit idle counter (DIC) for optimized performance with minimum IPG for local area network (LAN) applications
User interface that provides 64-bit direct interface with handshaking signals to ease connection to FIFOs. (MorethanIP also offers an optional asynchronous FIFO module that connects seamlessly to this interface and provides clock and rate decoupling).
Status word available with each frame on the user interface, providing information such as frame length, VLAN frame type indication, and error information
Preamble and start-of-frame delimiter (SFD) insertion and deletion
Optional padding termination and insertion for NIC applications, and forwarding of unmodified frames for switching applications
Optional support for 4-byte tag-extended frames before the frame destination MAC address
Programmable internal XGMII loopback
Implementation of statistics and event signals providing support for IEEE 802.3 basic and mandatory managed objects, as well as IETF Management Information Base (MIB) package (RFC2665) and remote network monitoring (RMON) required in simple network management protocol (SNMP) environments

Description
The 10 Gigabit Ethernet MAC Core complies with the IEEE 802.3ae specification, meeting the specificatio's requirements for WAN, LAN, and metropolitan area network (MAN) connectivity. The second version of the core can be used in both NIC or Ethernet switching applications. A set of configuration pins is available to dynamically set the core to terminate and form MAC frames (for NIC applications), or pass the frames without modification to the user application or Ethernet line (for switching applications).

Whether used for a NIC or a switching application, the 10 Gigabit Ethernet MAC Core provides support for IEEE-managed objects and IETF MIB-II object definitions, and RMON for management applications such as SNMP. It can also implement a flexible FIFO interface that connects seamlessly to any MorethanIP standard telecommunications interface, including SPI-4 and POS-PHY L4.

For Ethernet line applications, users can configure the core to implement either a XGMII or a XAUI when a design is targeted to an Altera® Stratix™ GX FPGA. Users can select the XGMII interface for integrating the core, together with custom logic, in an FPGA solution. Alternatively, the XAUI interface provides a simple 16-bit, board-level interface to connect the MAC to a physical device (such as a Xenpak 2.0 optical module)."