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"Features
Implements the full 802.3 specification with preamble / SFD generation, frame padding generation, cyclic redundancy code (CRC) generation and checking on transmit and receive respectively
Supports dynamically programmable 10Mbps, 100Mbps, and 1000Mbps operation
Supports full-duplex or half-duplex operation selectable via a Core configuration option
Seamless interface to commercial Fast Ethernet PHY device via a 4-Bit Medium Independent Interface (MII) operating at 25MHz
32-Bit Avalon™ Streaming Bus System On a Chip (SOC) interfaces allowing for efficient direct memory access (DMA) transactions
32-Bit Avalon System Interface with separate slave ports for data and control
Programmable frame maximum length providing support for any standard or proprietary frame length (e.g. 9K-Bytes Jumbo Frames)
Statistics indicators for frame traffic as well as errors (alignment, CRC, length) and pause frames providing for IEEE 802.3 basic and mandatory Management Information Database (MIB) package as well as Ethernet MIB (RFC 2665) and Remote Network Monitoring (RFC 2819) enabling implementation in simple network management protocol (SNMP) management environments
Includes data path first-in first-outs (FIFOs) with fully programmable depth and threshold levels ensuring data rates of 1Gbps with full back-to-back frame transfer support
The MAC is fully integrated in Altera's SOPC Builder with supporting files for easy system configuration and generation
C Software drivers and example applications
Protocol Acceleration Functions
Operates on transmission control protocol/Internet protocol (TCP/IP) and user datagram protocol/Internet protocol (UDP/IP) and Internet control message protocol/Internet protocol (ICMP/IP) data or IP header only
Support for IP and TCP, UDP, ICMP data for checksum generation and checking"