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"Features
Media access control (MAC) functions
UNH certified
Preamble and start-of-frame delimiter (SFD) insertion and deletion
Optional padding termination/insertion for NIC applications or forwarding of unmodified frames for switching applications
Support for virtual local area network (VLAN)-tagged frames according to IEEE 802.1Q specification in both transmit and receive functions
CRC-32 checking at full speed using a multi-stage, cyclic redundancy code
(CRC) calculation architecture with optional forwarding of the frame check sequence (FCS) field to the user application
CRC-32 generation and append on transmit or forwarding of user application provided FCS selectable on a per-frame basis
Per channel individual unicast MAC address for frame filtering or fully transparent operation
Programmable frame length to support standard and proprietary frame lengths
Embedded programmable multicast address resolution hash table
Programmable half duplex out, full duplex network operation (10/100 Mbps)
Half duplex collision and automatic frame re-transmission with jamming and back-off timer
Optional automatic pause frame generation from programmable first-in first-out (FIFO) congestion thresholds or by dedicated command pin with programmable Quanta
Per channel programmable automatic Xon and Xoff flow control frame generations
Network statistics
IEEE 1588 support
Support for all IEEE 1588 frames
Reference clock can be chosen independently of the network speed
Software programmable precise time stamping of ingress frames and egress frames
Timer monitoring capabilities for system calibration and timing accuracy management
Precise time stamping of external events with programmable interrupt generation
Programmable event and interrupt generation for external system control
Hardware and software controllable timer synchronization
Development boards
Standard Altera® CycloneTM II, Stratix®, and Stratix II FPGA prototyping and development boards
Comprehensive 10/100 and 10/100/1000 Ethernet PHY board selection"