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Apr 26 2010 8:00 amApr 29 2010 6:00 pmWhere:The San Jose McEnery Convention Center, San Jose, CAESC is the fastest-growing embedded event in the world, with events happening year-round in locations as Silicon Valley, Boston, India, the UK and France.
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Tutorial
1-D Discrete Cosine Transform
The 1-D Discrete Cosine Transform IP core is used in a wide range of signal and image processing applications. It supports from 8 to 32 points in both the forward and inverse directions. The 1-D Discrete Cosine Transform (DCT) does not require power-on at initialization. This parameterizable core supports a signed and unsigned 8 to 24-bit input data format. The user may specify the degree of parallelism and make the tradeoff between FPGA logic resources and sample rate, in order to generate the optimal design.
Device Family Support
# Virtex-II Pro
# Virtex-II
# Virtex-E
# Virtex
# Spartan-IIE"
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