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AvaFEC Enhanced Forward Error Correction (EFEC)
IP Vendor:
Avalon Microelectronics, Inc.
IP Type:
Design IP Description:
Avalon's proprietary dual BCH Enhanced Forward Error Correction (EFEC). Using a patent pending Avalon coding algorithm this code can acheive 56G throughput for 112G (2x56G) with >8.3dB gain in current FPGA technology.
Avalon's proprietary dual BCH Enhanced Forward Error Correction (EFEC). Using a patent pending Avalon coding algorithm this code can acheive 56G throughput for 112G (2x56G) with >8.3dB gain in current FPGA technology.
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