Virtex-5: Power-Up Ramp Times

The Virtex-5 FPGA family has rules about power-up ramp times outlined in Table 6 on Page 6 of the DC & Switching specifications:

On the face of it, the Virtex-5 spec claims that these special power-up ramp times apply to ALL power forms (VCCint, VCCaux, VCCo). However, we suspect that they're really intended for VCCint & VCCaux, and probably irrelevent for VCCo (Xilinx is just covering their arse by making a blanket application to all VCC's?).

Since we're finding it difficult to create room on the PWB for all of the special "soft start" Linear* Regulators to handle all of the power supplies for our Virtex-5, we were wondering if anyone else can confirm or deny the efficacy in taking shortcuts with the VCC__ ramp times (VCCint & VCCaux = ramp-rate important; VCCo = not so much). i.e., Did your volume/production (not onesies-twosies) Virtex-5 design work while violating power-up ramp times for one or more VCC's?

Your thoughts & experiences are appreciated.

* (our application can not tolerate Switching Regulators)

Facebook  Twitter  Linkedin  YouTube      RSS


Check out FPGA related videos

Find Us On Facebook