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VHDL - How to declare global variables???? Please help!!!
Hi!
Hey, im new to VHDL. I need some help from you, if u can. I have written some entities separately and the entities use certain variables. I now need to create a top level entity which included all these lower level entities. The thing is, some of the variables needs to be accessed by all these entities, ie, something like a global variables we use in C.
Like for example, if im creating a calculator, iv defined the addition, subtraction, mul as different entities, now they must all be access and write their value to a single variable called result.
How can i do this using VHDL? Can u please give me some suggestions?
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hello I think it is better
hello
I think it is better to define a Signal in your top level entity and also give each component a output port with that name, Exactly a mechanism like a bus.
- Hamze