Translation Error Ngdbuild 604 in ISE 9 2i.

I am doing project for viterbi decoder. I am successfully able to synthesize my code. but, while translating i am getting errors as follows :

NgdBuild:604 - logical block 'controlleru' with type 'controller' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'controller' is not supported in target 'virtex2'.

NgdBuild:604 - logical block 'msbu' with type 'msb' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, or the misspelling of a type name. Symbol 'msb' is not supported in target 'virtex2'.

My top module is as follows:
library ieee;
use ieee.std_logic_1164.all;
-- This is the top viterbi decoder.
entity viterbi is
port(clk,start_out : in std_logic;
data_out,term_out : out std_logic
);
end viterbi;

architecture struct of viterbi is

component encoder
port(data_in,reset,clk : in std_logic;
i0,i1,i2 : out std_logic_vector(2 downto 0)
);
end component;

component controller
port(clk_w0,start : in std_logic;
clk_mp,clk_encoder : out std_logic;
reset_encoder,reset_mpl : out std_logic;
reset_PM,reset_p2s,reset_comp_carry : out std_logic);
end component;

component pointer
generic (reset_value : integer :=0);
--0 is just the default value;
port(msb : in std_logic_vector(7 downto 0);
clk,reset,new_bit : in std_logic;
pointer_out : out std_logic_vector(7 downto 0)
);
end component;

component acstosm_mux
port(clk,reset : in std_logic;
decision_in : in std_logic_vector(0 to 255);
termination_in : in std_logic_vector(0 to 255);
pointer : in std_logic_vector(7 downto 0);
decision_out,termination_out : out std_logic
);
end component;

component bmu
port (i0,i1,i2 : in std_logic_vector(2 downto 0);
bmu000,bmu001,bmu010,bmu011,bmu100,bmu101,bmu110,
bmu111 : out std_logic_vector(4 downto 0));
end component;

component p2s_block
port(reset,clk : in std_logic;
bmu000,bmu001,bmu010,bmu011,bmu100,bmu101,bmu110,
bmu111 : in std_logic_vector(4 downto 0);
BM: out std_logic_vector(0 to 7)
);
end component;

component acsu_block
port(BM,msb_BMjp : std_logic_vector(0 to 7);
clk,reset_carry : in std_logic;
comp_enable,reset_PM : in std_logic;
term,dec : out std_logic_vector(0 to 255)
);
end component;

component msb
port(clk,reset : in std_logic;
msb : out std_logic_vector(7 downto 0)
);
end component;

component lfsr
port(clock : std_logic;
reset : std_logic;
data_out : out std_logic
);
end component;

signal reset_mpl,reset_PM,reset_p2s,reset_encoder,dec_internal : std_logic;
--signal status : std_logic;
signal data_random,reset_comp_carry,clk_mp,clk_encoder : std_logic;
signal dec,term : std_logic_vector(0 to 255);
signal BM : std_logic_vector(0 to 7);
signal msb_BMjp : std_logic_vector(0 to 7);
signal msb_signal,pointer_internal : std_logic_vector(7 downto 0);
signal bmu000,bmu001,bmu010,bmu011,bmu100,bmu101,bmu110,
bmu111 : std_logic_vector(4 downto 0);
signal i0,i1,i2 : std_logic_vector(2 downto 0);
signal start : std_logic;
begin
start<=not(start_out);

lfsru : lfsr port map (clk_mp,start,data_random);

controlleru : controller port map(clk,start,clk_mp,clk_encoder,reset_encoder,reset_mpl,reset_PM,reset_p2s,reset_comp_carry);
encoderu : encoder port map(data_random,reset_encoder,reset_p2s,i0,i1,i2);
bmuu : bmu port map ( i0=>i0,
i1=>i1,
i2=>i2,
bmu000=>bmu000,
bmu001=>bmu001,
bmu010=>bmu010,
bmu011=>bmu011,
bmu100=>bmu100,
bmu101=>bmu101,
bmu110=>bmu110,
bmu111=>bmu111);
pointeru : pointer generic map(0)
port map( msb_signal,clk_mp,reset_mpl,dec_internal,
pointer_internal);
acstosmu : acstosm_mux port map(reset_comp_carry,reset_mpl,dec,term,pointer_internal,
dec_internal,term_out);
p2s_blocku : p2s_block port map(reset_comp_carry,clk,bmu000,bmu001,
bmu010,bmu011,bmu100,bmu101,bmu110,bmu111,BM);
acsu_blocku : acsu_block port map (BM=>BM,
msb_BMjp=>msb_BMjp,
clk=>clk,reset_carry=>reset_comp_carry,
comp_enable=>clk_encoder,reset_PM=>reset_PM,
term=>term,dec=>dec);
process(bmu000,bmu001,bmu010,bmu011,bmu100,bmu101,bmu110,bmu111,reset_comp_carry,
msb_BMjp,start)
begin
if start = '1' then
msb_BMjp<="00000000";
elsif reset_comp_carry = '0' and reset_comp_carry'event then
msb_BMjp(0)<=bmu000(4);
msb_BMjp(1)<=bmu001(4);
msb_BMjp(2)<=bmu010(4);
msb_BMjp(3)<=bmu011(4);
msb_BMjp(4)<=bmu100(4);
msb_BMjp(5)<=bmu101(4);
msb_BMjp(6)<=bmu110(4);
msb_BMjp(7)<=bmu111(4);
end if;
end process;
msbu : msb port map(clk_mp,reset_mpl,msb_signal);
data_out<=dec_internal;
end struct;

So what does this mean ?
i am not able to simulate my work, is there any way to solve this?
Thanks

Facebook  Twitter  Linkedin  YouTube      RSS

 

Check out FPGA related videos

Find Us On Facebook