I tried to do simulation of MCB example design on sp601 xilinx board.(spartan 6, DDR2 memory)
I can run it on chip scope.
I am running isim simulator.
I have been trying for almost 3 days.
I could see values for other signals but for data bus.. zzzzzzzzz.(except some times i see 000..fff)
I dont know what i am doing wrong...
Is the version of simulator matter?
VHDL design with verilog memory model matters???