Release: FloPoCo 2.2.0 - Arithmetic Core Generator for FPGAs

Dear colleagues,

We are proud to announce the release of FloPoCo 2.2.0.

FloPoCo is an open-source arithmetic core generator for FPGAs.

Its main features are:
- support of integer, fixed-point, floating-point and LNS arithmetics
- a growing range of operators, including meta-operators
such as multiplications by constants and polynomial approximators,
- synthesizable VHDL output,
- frequency-directed automatic pipelining,
- generated code is transparently optimized for a range of targets
(Altera or Xilinx)

Under the hood, FloPoCo is also a C++-based core generator framework
that clearly separates the functionality (embedded as combinatorial
VHDL) and the pipelining (handled automatically by the framework,
producing correct-by-construction pipelines). It is easy to extend
for the VHDL-literate.

This release features a few new operators and many improvements to
existing ones. It is also the first release to include the FPPipeline
meta-operator that, from a dataflow program in C-like syntax,
assembles a floating-point pipeline implementing it for a
user-specified precision and frequency.

More details on

We welcome feedback and bug reports.

The FloPoCo team

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