problem with a fpga in a ts7300 board

Hello everyone:
Im programming a FPGA Cyclone II in a ts7300 board, I started to program from
ts7300_top file which controls the FPGA devices attached to it, Im using Quartus II and everything worked out, I was able to compile without any problem. Now I'm having
a problem, when I loaded the new .rbf file the board start to fail,
the serial console doesn't work anymore. Its connected to serial1 port
and I'm not able to write anything through it and when I try to load
remotely a .rbf file again,
I get this error:

[email protected]:/home/yulliel# load_ts7300 ts7300_top.rbf
load_ts7300: FPGA load failure: 72

Here is what I get with the dmesg command:

TS-UART/7300 detected a TS-7300 board
registering c03b3d60,c03b3e60
ttyT8S0 at MMIO 0x72000000 (irq = 40) is a TSUART
WARNING: port 0 failed STAT sanity check!
ttyT9S0 at MMIO 0x72000000 (irq = 40) is a TSUART
WARNING: port 0 failed STAT sanity check!
registering c15ea080,c15ea180
ttyT8S1 at MMIO 0x72000004 (irq = 40) is a TSUART
WARNING: port 1 failed STAT sanity check!
ttyT9S1 at MMIO 0x72000004 (irq = 40) is a TSUART
WARNING: port 1 failed STAT sanity check!
registering c15ea280,c15ea380
ttyT8S2 at MMIO 0x72000008 (irq = 40) is a TSUART
WARNING: port 2 failed STAT sanity check!
ttyT9S2 at MMIO 0x72000008 (irq = 40) is a TSUART
WARNING: port 2 failed STAT sanity check!
registering c15ea480,c15ea580
ttyT8S3 at MMIO 0x7200000c (irq = 40) is a TSUART
WARNING: port 3 failed STAT sanity check!
ttyT9S3 at MMIO 0x7200000c (irq = 40) is a TSUART
WARNING: port 3 failed STAT sanity check!
registering c15ea680,c15ea780
ttyT8S4 at MMIO 0x72000010 (irq = 40) is a TSUART
WARNING: port 4 failed STAT sanity check!
ttyT9S4 at MMIO 0x72000010 (irq = 40) is a TSUART
WARNING: port 4 failed STAT sanity check!
registering c15ea880,c15ea980
ttyT8S5 at MMIO 0x72000014 (irq = 40) is a TSUART
WARNING: port 5 failed STAT sanity check!
ttyT9S5 at MMIO 0x72000014 (irq = 40) is a TSUART
WARNING: port 5 failed STAT sanity check!
registering c15eaa80,c15eab80
ttyT8S6 at MMIO 0x72000018 (irq = 40) is a TSUART
WARNING: port 6 failed STAT sanity check!
ttyT9S6 at MMIO 0x72000018 (irq = 40) is a TSUART
WARNING: port 6 failed STAT sanity check!
registering c15eac80,c15ead80
ttyT8S7 at MMIO 0x7200001c (irq = 40) is a TSUART
WARNING: port 7 failed STAT sanity check!
ttyT9S7 at MMIO 0x7200001c (irq = 40) is a TSUART
WARNING: port 7 failed STAT sanity check!

The register with warnings are the ones of the FPGA MAC core 32-bit
registers according to the Memory and Register Map.
I already restarted the board and I get the same problems, any suggestion?
What is the way to unload programs already loaded at the FPGA?

Any help will be appreciated

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