good day to all. i'm new in FPGA designing.. i hve a problem in displaying my data in the lcd of spartan 3e board... can anyone help me.. here is my code..
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test5 is
Port ( clk : in STD_LOGIC;
LCD_E : out std_logic;
LCD_RW : out std_logic;
LCD_RS : out std_logic;
starta_ce : out std_logic;
starta_oe : out std_logic;
starta_we : out std_logic;
dataout : out std_logic_vector (3 downto 0));
end test5;
architecture Behavioral of test5 is
-- declaring type of types
--
type state_type is ( boot, function_set, write_dd, set_ddr, display_clear,
Display_control, Entry_mode);
--
-- declaring signals
--
signal state : state_type;
--
begin
process (clk) is
variable count : integer := 0;
begin
-- disable the starta to prevent interference
--
starta_oe <= '1';
starta_ce <= '1';
starta_we <= '1';
--
lcd_rw <= '1';
lcd_rs <= '0';
--if clk'event and clk = '1' then
case state is
when boot =>
if count = 1500000 then -- wait >= 15 ms (i set 30 ms)
dataout <= "0011";
count := count + 1;
elsif count = 5 then -- wait 100 ns before lcd e goes high
lcd_e <= '1';
count := count + 1;
elsif count = 1500025 then -- wait 440 ns before lcd e goes low
lcd_e <= '0';
count := count + 1;
elsif count = 1910005 then
lcd_e <= '1';
count := count + 1;
elsif count = 1910010 then -- wait for >= 4.1 ms (i set 8.2 ms)
dataout <= "0011";
count := count + 1;
elsif count = 1910030 then
lcd_e <= '0';
count := count + 1;
elsif count = 1920005 then
lcd_e <= '1';
count := count + 1;
elsif count = 1920010 then -- wait for >= 100us (i set 200 us)
dataout <= "0011";
count := count + 1;
elsif count = 1920030 then
lcd_e <= '0';
count := count + 1;
elsif count = 1924005 then
lcd_e <= '1';
count := count + 1;
elsif count = 1924010 then -- wait for >= 40 us ( i set 80 us)
dataout <= "0010";
count := count + 1;
elsif count = 1924030 then
lcd_e <= '0';
count := count + 1;
elsif count = 192800 then -- wait for >= 40 us ( i set 80 us)
state <= function_set;
count := 0;
else
count := count + 1;
end if;
when function_set =>
if count = 5 then
lcd_e <= '1';
dataout <= "0010"; -- upper nibble
count := count + 1;
elsif count = 55 then -- wait for 2 us
dataout <= "1011"; -- lower nibble
count := count + 1;
elsif count = 80 then
lcd_e <= '0';
count := 0;
state <= entry_mode;
else
count := count + 1;
end if;
when Entry_mode =>
if count = 5 then
lcd_e <= '1';
dataout <= "0000"; -- upper nibble
count := count + 1;
elsif count = 55 then -- wait for 2 us
dataout <= "0110"; -- lower nibble
count := count + 1;
elsif count = 80 then
lcd_e <= '0';
count := 0;
state <= Display_control;
else
count := count + 1;
end if;
when Display_control =>
if count = 5 then
lcd_rs <= '1';
dataout <= "0000"; -- upper nibble
count := count + 1;
elsif count = 55 then -- wait for 2 us
dataout <= "1101"; -- lower nibble
count := count + 1;
elsif count = 80 then
lcd_e <= '0';
count := 0;
state <= display_clear;
else
count := count + 1;
end if;
when display_clear =>
if count = 5 then
lcd_e <= '1';
dataout <= "0000"; -- upper nibble
count := count + 1;
elsif count = 55 then -- wait for 2 us
dataout <= "0001"; -- lower nibble
count := count + 1;
elsif count = 80 then
lcd_e <= '0';
count := count + 1;
elsif count = 4000 then
state <= set_ddr;
count := 0;
else
count := count + 1;
end if;
when set_ddr =>
if count = 5 then
lcd_e <= '1';
dataout <= "1000"; -- upper nibble
count := count + 1;
elsif count = 55 then -- wait for 2 us
dataout <= "0000"; -- lower nibble
count := count + 1;
elsif count = 80 then
lcd_e <= '0';
count := 0;
lcd_rs <= '1';
state <= write_dd;
else
count := count + 1;
end if;
when write_dd =>
if count = 5 then
lcd_e <= '1';
dataout <= "0011"; -- upper nibble
count := count + 1;
elsif count = 55 then -- wait for 2 us
dataout <= "0000"; -- lower nibble
else
count := count + 1;
end if;
end case;
end process;
end Behavioral;
thank you.