mad FIFO

hi,

I AM SCREAMING FOR HELP,

HELPPP HELP HELP

again

HEEELPPPPPPPPPP

I need a synthesizable FIFO that does not take consequetive duplicate words. for that purpose, i wrote a verilog code which gives fine result in simulation--

here it is-

module fifo_8(clk, rstp, din, writep, readp, dout, emptyp, fullp);

parameter bits=3;

parameter DEPTH = 3, // 2 bits, e.g. 4 words in the FIFO.
MAX_COUNT = 3'b111; // topmost address in FIFO.

input clk;
input rstp;
input [bits:0] din;
input readp;
input writep;
output [bits:0] dout;
output emptyp;
output fullp;

reg emptyp;
reg fullp;

// Registered output.
//reg [bits:0] dout;

// Define the FIFO pointers. A FIFO is essentially a circular queue.
//
reg [(DEPTH-1):0] tail;
reg [(DEPTH-1):0] head;

FIFO_MEM_BLK memblk(.clk(clk),
.writeN(writep),
.rd_addr(tail),
.wr_addr(head),
.data_in(din),
.data_out(dout)
);

always @(din[bits:0])
begin

if(rstp)head=0;
else if (writep == 1'b1 && fullp=0) begin
head = head + 1;
end

// Update the tail register.
//
always @(posedge clk) begin

if (rstp == 1'b1) begin
tail = 0;
end
else begin
if (readp == 1'b1 && emptyp == 1'b0) begin
// READ
tail = tail + 1;
end
end
end

always @(posedge clk)
begin
if((head-tail)==2'b01)
emptyp=1;
else emptyp=0;

if((head-tail)==MAX_COUNT)
begin
fullp=1;
end
else fullp=0;
end
endmodule

module FIFO_MEM_BLK( clk,
writeN,
wr_addr,
rd_addr,
data_in,
data_out
);

parameter bits=3;

parameter DEPTH = 3, // 2 bits, e.g. 4 words in the FIFO.
MAX_COUNT = 3'b111; // topmost address in FIFO.

input clk; // input clk.
input writeN; // Write Signal to put data into fifo.
input [DEPTH-1:0] wr_addr; // Write Address.
input [DEPTH-1:0] rd_addr; // Read Address.
input [bits:0] data_in; // DataIn in to Memory Block

output [bits:0] data_out; // Data Out from the Memory
// Block(FIFO)

wire [bits:0] data_out;

reg [bits:0] FIFO[0:MAX_COUNT];

assign data_out = FIFO[rd_addr];

always @(posedge clk)
begin
if(writeN==1'b1)
begin
FIFO[wr_addr] = data_in;
end
end

endmodule

//////////////////////////////////////////////////////////////////////////////////

But, when i try to work with my XUPV2P board, it doesn't work.
I think the problem is with--

// always @(din[bits:0])

is it not synthesizable?
I tried with a temporary register, which failed to deliver the goods..

where is the bug?

please please help

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