Logic implementation prb

 Hey i am using ise 9.1i for synthesizing my designs for spartan 3 fpgas. I am facing a very wierd problem.

My system comprises of 1 xcs400 fpga and an ARM 7 processor. My RTL design is very modular. Here is the problem.

 

I have a microcontroller interface in my rtl design to communicate with arm. other portions of my rtl design are related to some other logic implementations.now what happens is that when i change some line of code or logic in the other modules WHICH ARE IN NO WAY CONNECTED TO CONTROLLER INTERFACE, the bit file that is generated causes my processor to crash and go into abort conditions. this happens primarily because of contention on the data bus of the processor.

However, i cannot tell why this is happening that a change in logic is some very remote part of the design causes the controller interface to misbehave. Keep in view that my controller interface is perfected and is running perfectly on a couple of other systems.the only difference between a working bit file and a non working bit file is a small change in some other part of the design and it is so small that it may include only a size change of a register.

 

i have pulled down all unused ios and all other setups are exactly the same

 

Regards

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