Hurry-up, Join Part-time VLSI Course offer by Cadence & UCSC @ Bangalore



TIIT is  a wholly owned subsidiary of Time To Market Inc, U.S.A. Since 1999.


What is Time To Market Inc?


Time To Market Inc. (TTM)( is an ASIC and FPGA service provider. TTM provides the most cost-effective, reliable and dependable path to take customer's concept to silicon. TTM provides a seamless interface between the customer and all the other partners involved in taking the customer's netlist to a Packaged IC.


Keeping in mind the demand that has spurred the semiconductor industry in India, TTM, UCSC Extension, and Cadence Design Systems have decided to work together to come up with a comprehensive training program in VLSI to address the growing demand for skilled VLSI professionals. World-class technology experts, curriculum, and EDA tools back the training program. The main goal of the training program is to provide the semiconductor industry with a skilled work force, and also to provide an opportunity for the existing work force to gain new skills and be part of the growing semiconductor industry in India



Certificate Program in VLSI Logic Design and Layout Design Engineering.

TIIT (TTM Institute of Information Technology) in collaboration with the University Of California at Santa Cruz Extension in the Silicon Valley and Cadence Design Systems offers a certificate program in VLSI design engineering. Students who complete the required courses with minimum grade point average (GPA) will be awarded a certificate in VLSI design engineering (Physical Design or Logic Design) from the University Of California Santa Cruz extension in Silicon Valley.


Transfer your credits: After completion of the course you can transfer 12 Credits to your higher studies in USA with the University Of California at Santa Cruz Extension in the Silicon Valley.


Course: Updated Exclusive courses for Layout Design & Logic Design Engineering. 

Duration:  Will be for 20 weeks. 

Class Timings: Classes will be during the weekends; 6 days Lab will be open to work on Tools. 

Fees: 90k for Layout Design Course. 70k for Logic Design Course.

Payment Flexibility: Can pay it in 3 Installments. 

Instructors: : Tools are taught by experienced working professionals.

Placement Statistics:  90% of the people got employed in VLSI Industry so far. Placement Assistance will be provided, and setting up mock interviews, resume building, seminar series etc will be provided. 

Batch Start Date: 22nd December 2007 at Bangalore.

Prerequisites:BE/BTech/ME/MTech/MSc in either computer science or Electrical/Electronics 

Registrations: Open Online @ ( for Bangalore. 

Screening Test: You have to take screening test comprises of basic digital electronics & Aptitude. Multiple-choice question.


Make sure: TIIT’s Intake is  20 Students per batch, we are getting advance booking for Batches; make sure you will get the seat.


For more info: : 


TIIT Pvt,Ltd.

18,1st Floor,Palavalli Plaza.

100 feet ring road.2nd stage,

BTM Layout. Bangalore-76

Tel: +91-08-26789654.

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