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How to Clock any lattice's FPGA....
October 18, 2007 - 6:03am — Anuja
How to Clock any lattice's FPGA....
should i use any port pin or sp function pin... or only those pins having PLL clk as dual function???
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There are special purpose
There are special purpose pins for the devices that you are using to clock lattice device. It would depend ont he lattice device that you use, to find out what exact device you are using. Let me know the device that you are using and may be I can help with a solution.
Lattice
hey its from EC1 family very basic device.....
Got it, go to the following
Got it, go to the following data sheet and page number 67 (also page 4-1).
http://www.latticesemi.com/lit/docs/datasheet...
Here is the list of signal description that would mean clock:
PLL and Clock Functions (Used as user programmable I/O pins when not in use for PLL or clock pins)
[LOC][num]_PLL[T, C]_IN_A I Reference clock (PLL) input pads: ULM, LLM, URM, LRM, num = row from
center, T = true and C = complement, index A,B,C...at each side.
[LOC][num]_PLL[T, C]_FB_A I Optional feedback (PLL) input pads: ULM, LLM, URM, LRM, num = row from
center, T = true and C = complement, index A,B,C...at each side.
PCLK[T, C]_[n:0]_[3:0] I Primary Clock pads, T = true and C = complement, n per side, indexed by
bank and 0,1,2,3 within bank.
Hope that helps.
Lattice clocking
Thanks a lot for suggesting a nice guideline regarding clocking.
my one more doubt is:-can I use a port pin which is not having clock as dual function.That means a pin which not belongs to PLL module.