Device LUT utilization is too high : 107% !!! .. how can I optimize that ?

Hi guys ..

I'm trying to synthesize my VHDL design using XST and it's taking forever, i.e. it never completes synthesis up to the generation of the netlist .. for that, I decided to try Synplify (ver. 2009.6SP1) .. it took around 30 mins to complete the synthesis .. but the LUT utilization is too high .. 107%!!!! .. i.e., the design won't fit in the device .. I tried to map this netlist and, as expected, it didn't map as the utilization is more than 100% ..

There is another problem that I'm using an IP whose utilization doesn't show up during synthesis .. for that I even want to optimize my design to maybe 75% or even less to leave some space for the IP as well ..

Is there any way to optimize the number of mapped LUTs ? .. can I map them to the unused RAM blocks? .. given that I didn't use any BRAM or DRAM in my design ..

P.S. my target device is Spartan-3A DSP 1800A .. and I'm using ISE 11.2