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CPLD output
I am developing a digital card with XC9572 CPLD. 48MHz clock from an oscillator is provided. I have implemented a simple VHDL code to divide the main clock to a lower frequency. When I observe the output on one of the I/O pins, I see kind of a noise which is in the form of "waves". The signal changes in a wavy manner with highs and lows. I tried many methods to overcome this noise but in vain. So please give me your suggestions.
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