conveting matlab code into vhdl code

Hi!

I am writing synthesizable Matlab for Xilinx FPGA. They have a technology called AccelDSP, which takes a flavour of Matlab and translates it into HDL. The same technology is available in Xilinx System Generator inside a block called M-code. In fact, there is a way to write Matlab, which mimics the way one would write HDL. It's more a matter of style reather than language.

Below is an example from an M-code block in System Generator.

function [sect_1_written, sect_2_written, addr_out, data_out, we_out, ena_out] = D_Write_addr_SM(Sect_1_empty, Sect_2_empty, decry_1, decry_2, addr_in, pckt_end, byte3_in, dv_in, data_in, rst)

%% This file is a Write State Machine

%% States declaration

idle = 0
write_section_1 = 1;
write_section_2 = 2;

%% The state is a 2-bit register

persistent state, state = xl_state(idle, {xlUnsigned, 2, 0});

%% Registered outputs

persistent addr_out_q, addr_out_q = xl_state(0, {xlUnsigned, 9, 0});
persistent we_out_q, we_out_q = xl_state(false, {xlBoolean});
persistent data_out_q, data_out_q = xl_state(0, {xlUnsigned, 8, 0});
persistent ena_out_q, ena_out_q = xl_state(false, {xlBoolean});
persistent sect_1_written_q, sect_1_written_q = xl_state(0, {xlUnsigned, 1, 0});
persistent sect_2_written_q, sect_2_written_q = xl_state(0, {xlUnsigned, 1, 0});
%persistent writing_sect1_q, writing_sect1_q = xl_state(false, {xlBoolean});
%persistent writing_sect2_q, writing_sect2_q = xl_state(false, {xlBoolean});
persistent wrote_sect1, wrote_sect1 = xl_state(false, {xlBoolean});

%% process begin -implies clk rising edge

% update states & outputs

addr_out = addr_out_q;
we_out = we_out_q;
data_out = data_out_q;
ena_out = ena_out_q;
sect_1_written = sect_1_written_q;
sect_2_written = sect_2_written_q;
% writing_sect1 = writing_sect1_q;
% writing_sect2 = writing_sect2_q;
wrote_sect1 = wrote_sect1;

if rst % reset

we_out_q = false;
addr_out_q = 0;
data_out_q = 0;
ena_out_q = false;
% writing_sect1_q = false;
% writing_sect2_q = false;
%state_out = 0;

else

switch double(state)

case idle
% state_out = 0;
% writing_sect1_q = false;
% writing_sect2_q = false;
we_out_q = false;
ena_out_q = false;
sect_1_written_q = 0;
sect_2_written_q = 0;

if Sect_1_empty && decry_1 && ~wrote_sect1

state = write_section_1;

elseif Sect_2_empty && decry_1 && wrote_sect1

state = write_section_2;

else
state = idle;
end

case write_section_1
% state_out = 1;
% writing_sect1_q = true;
we_out_q = true; % writing_sect1_q;
addr_out_q = addr_in;
data_out_q = data_in;
ena_out_q = dv_in && decry_2;
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There is another tool which will convert the codes from MATLAB/ Simulink to HDL. I read about it in the Altera website. I have not worked with it. Believe it is possible to control the design directly from the MATLAB...