7-SEGMENT DRIVER

Hi, I'm newbie in FPGA. I wont to write the 7-SEG driver for my board. There is SPARTAN-3E in it. I have some problems with ISE. 

 

This is my VHDL code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity dfg is
port (SEG : OUT STD_LOGIC_VECTOR (0 to 7);
AN : OUT STD_LOGIC_VECTOR (0 to 3);
CLK: IN STD_LOGIC);
type S_VAL is ('1','2','3','4','5','6','7','8','9','0','A','B');
type S_VAL_ARR is array (natural range <>) of S_VAL;

end dfg;
architecture Behavioral of dfg is
signal counter : integer range 0 to 200_010 := 0;
signal counter2 : integer range 0 to 15 := 0;
signal val : S_VAL_ARR (0 to 3);
--??????? ????????????? ???????? ? ??????? ??????????????? ???????
function SST (INP_VAL : S_VAL) return STD_LOGIC_VECTOR is
begin
if INP_VAL = '1' then return "10011111";
elsif INP_VAL = '2' then return "00100101";
elsif INP_VAL = '3' then return "00001101";
elsif INP_VAL = '4' then return "10011001";
elsif INP_VAL = '5' then return "01001001";
elsif INP_VAL = '6' then return "01000001";
elsif INP_VAL = '7' then return "00011111";
elsif INP_VAL = '8' then return "00000001";
elsif INP_VAL = '9' then return "00001001";
elsif INP_VAL = 'A' then return "00010001";
else return "00000000";
end if;
end SST;
begin
val<="12AB";
process(CLK)
begin
if ( CLK'event and CLK = '1' ) then
counter <= counter+1 ;
if ( counter = 200_000 ) then
counter <= 0;
counter2 <= counter2 + 1;
if (counter2 = 1) then 
AN <="0111";
SEG <= SST(val(0));
elsif (counter2 = 2) then 
AN <="1011";
SEG <= SST(val(1));
elsif (counter2 = 3) then 
AN <="1101";
SEG <= SST(val(2));
elsif (counter2 = 4) then 
AN <="1110";
SEG <= SST(val(3));
else counter2<=0;
end if;
else null;
end if;
else null;
end if;
end process ;
end Behavioral;
 

and I received the message:

WARNING:Xst:1610 - "/home/dinya/Projects/FPGA/ghdfghd/SEVEN_SEG.vhd" line 61: Width mismatch. <val> has a width of 16 bits but assigned expression is 32-bit wide.
WARNING:Xst:1710 - FF/Latch <AN_3> (without init value) has a constant value of 0 in block <dfg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <AN_2> (without init value) has a constant value of 0 in block <dfg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <AN_1> (without init value) has a constant value of 0 in block <dfg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <AN_0> (without init value) has a constant value of 0 in block <dfg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <AN_3> (without init value) has a constant value of 0 in block <dfg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <AN_2> (without init value) has a constant value of 0 in block <dfg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <AN_1> (without init value) has a constant value of 0 in block <dfg>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <AN_0> (without init value) has a constant value of 0 in block <dfg>. This FF/Latch will be trimmed during the optimization process.
WARNING:PhysDesignRules:367 - The signal <CLK_IBUF> is incomplete. The signal
does not drive any load pins in the design.

WARNING:Par:288 - The signal CLK_IBUF has no load. PAR will not attempt to route this signal.
WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

 

I don't understand what does it mean. How can I resolve this problem?

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