Mentor Forum for Verification - Crossing the barrier to Advanced Functional Verification - Sophia Antipolis, France

Overview

Traditionally FPGA design flows do not include large amounts of verification prior to heading into the lab. Today’s FPGA devices however, are growing dramatically in both size and complexity such that FPGA design teams verification needs almost match those previously reserved for ASIC design.

For FPGA the worry is not about errors and tape out costs but extended debug times in the lab resulting in unpredictable schedules and unacceptable costly and difficult to debug failures in the field.

Compared to the ASIC world, FPGA team have historically invested less time and money adopting new verification methodologies and tools, particularly when productivity results are not immediately apparent.

Who Should Attend

FPGA design and verification engineers and managers looking to understand how they could improve their FPGA verification environment with easy to adopt advanced techniques, flows and tools.

Agenda

09:00 Registration
09:30 Introduction
09:45 Questa 10.1 Update
10:30 Morning Coffee
10:45 Code Coverage
11:30 ABV for VHDL Design
12:15 Lunch
13:15 Automated Static Verification
14:00 Verification Management
14:45 Afternoon Coffee
15:00 Requirements Management for ISO-262 and DO-254

What You Will Learn

This seminar will focus on flows, methodologies and tools for FPGA verification that can be applied in steps to ease adoption or tools that are more automated. These solutions provide immediate measurable value in users flows and process ans help FPGA designers get to that next level of verification and quality.

Register to attend this seminar to learn what are the trends in the area of FPGA verification and how to boost your knowledge of the latest verification techniques and how they could be applied to your current and upcoming projects.