6th IEEE International Workshop on Design for Manufacturability & Yield (DFM&Y 2012) - San Francisco, CA
Increased manufacturing susceptibility in today’s nanometer technologies requires up to date solutions for yield optimization. In fact, designing an SoC for manufacturability and yield aims at improving the manufacturing process and consequently its yield by enhancing communications across the design – manufacturing interface. A wide range of Design-for-Manufacturability (DFM), Design-for-Yield (DFY) and Design-for-Test (DFT) methodologies and tools are proposed today. Some of these are leveraged during the back-end design stages, and others have post design utilization, from lithography up to 3D integration, wafer sort, packaging, final test and failure analysis. These solutions can dramatically impact the business performance of chip manufacturers. They can also significantly affect age-old chip design flows. Using a DFM/DFY/DFT solution is an investment and thus choosing the most cost effective one(s) requires trade-off analysis. The workshop will analyze key trends and challenges in DFM, DFY and DFT methodologies, and provide an opportunity to discuss a range of DFM, DFT and DFY solutions for SoC designs now and in the future, including practical case studies that demonstrate the successes and failures of such solutions.
Representative topics include, but are not limited to the following:
* Analog and Mixed-Signal DFM
* OPC and RET
* Test-Based Yield Learning
* 3D Integration
* Electrical, Design-Driven DFM
* System/Architecture Level
* Built-in Repair Analysis and Self-Repair
* Adaptive Design Techniques in DFM/DFY
* Statistical Design
* Process Monitoring IP
* Embedded Test and Diagnosis
* Design-Aware Manufacturing
* Variability Reduction Techniques
* Yield Enhancement IP
* Interconnect Variability
* Yield Management
Information for Authors:
To present at the Workshop, authors are invited to submit unpublished extended abstracts or full papers, 2 to 4 pages in length. Submissions on ambitious works in progress are also encouraged. Each submission should include a short abstract of 50 words, and keywords. The review process is blind. Please do not include author names or affiliations. Proposals for embedded tutorials and panel discussions are also invited.
The goal of the workshop is to foster unrestricted discussion in the field of design-manufacturing-yield-test interactions. Copies of papers will be provided to attendees in the form of Workshop Notes; however, no proceedings will be published. Therefore, accepted papers can still be submitted to other conferences and journals.
The DFM&Y workshop is sponsored by the IEEE Computer Society Test Technology Technical Council (TTTC) and the IEEE Council on Electronic Design Automation (CEDA).