Mentor Graphics U2U (User 2 User) Group - Santa Clara, CA

This all day meeting will include product roadmap and technical sessions on Calibre, Functional Verification, Silicon Test Solutions, Custom IC and AMS. Share your experiences with other engineers and understand how they have addressed similar challenges.

U2U Training Opportunities

Registration is now open! Attend U2U and receive a 20% discount on these NEW Calibre classes! For more information click on links below.

* Calibre Advanced Topics: nmLVS Debug Case Studies | June 10-11, 2009 | Mentor Graphics San Jose Office
* Calibre Advanced Topics: Mastering Calibre eqDRC | June 10-12, 2009 | Mentor Graphics San Jose Office

Abstracts:

* Calibre Track
* Custom IC/AMS Track
* Functional Verification Track
* Silicon Test & Yield Analysis (formerly DFT) Track

Additional information:

Cost: This session is offered free of charge. Complimentary refreshments including continental breakfast and lunch will be provided. However, participants are responsible for the own business travel expenses

Schedule: For your convenience, registration and continental breakfast wil begin at 8:00am. The session will start at 9:00am and end at approximately 4:30pm.

Agenda:

8:00am - 9:00am Breakfast
9:00am - 10:00am DFM at the Bleeding Edge: Making Design and Manufacturing Work - Walter Ng, Chartered Semiconductor Manufacturing

10:00am - 11:30am

Calibre nmLVS/xRCPMM Roadmap - Carey Robertson, Mentor Graphics

Silicon Test and Yield Analysis Update

What Do You Need to Improve your verification Throughput - Joe Rodriguez, Mentor Graphics

Custom IC Roadmap - Chris Cone, Mentor Graphics | AMS Roadmap - See-Mei Chan, Mentor Graphics
11:30am - 12:45pm Lunch

1:00pm - 1:50pm

Getting the Most of Smart Fill by Solving Density Requirements of 3 Different Layers at the Same Time - Norma Rodriguez, AMD
Test Pattern Generation Methods for Small Delay Defect Testing - Narendra Devta-Prasanna & Sandeep Goel, LSI
Corporation

1:00pm - 2:00pm

Time-to-Market Design Quality with Open Verification Methods (OVM) -Tom Fitzpatrick, Mentor Graphics

Update on Phasing into the New dmgr_ic - Ronnie Hunt, Advanced Bionics

1:50pm - 2:40pm
Advanced Physical Verification at 40nm: Calibre Best Practices -Kuldeep Singh, Sun Microsystems
Hierarchical DFT Implementation inIndustrial Design – Case Study - SaketKumar Goyal, LSI Corporation

2:40pm - 3:30pm
Ease of LVS Debugging with the New Improved Calibre RVE - Padma Musunuri, Micron & Lata Valluri, Mentor Graphics
Handling One-Hot Muxes in TestKompress - Henry Kang, Netxen

2:15pm -3:15pm
An Applied Low-Power Verification Methodology Using Questa PowerAware - Jennifer Leng, Marvell
Improve Full Chip Verification Performance of PCM Memory Design with Questa ADMS - Peng Zhang,Numonyx

3:30pm - 4:20pm
SPICE-correlated Verilog-AMS Behavioral Models for efficient validation
of system-level integration using Questa ADMS - Harry Wang, Actel
Clock-Domain-Crossings: Coverage Confidence in the face of Metastability - Dr. Ping Yeung,Mentor Graphics

4:30pm - 6:00pm Closing Reception & Raffle