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FPL '09 - The International Conference on Field Programmable Logic and Applications - Prague, Czech Republic

When: 
Aug 31 2009 - 3:30pm - Sep 2 2009 - 9:30pm
Where: 
Hotel Don Giovanni, Prague, Czech Republic
Event/Conference Information URL: 
Click here to register

The International Conference on Field Programmable Logic and Applications (FPL) is the first and largest conference covering the rapidly growing area of field-programmable logic. During the past 18 years, many of the advances achieved in reconfigurable architectures, applications, design methods and tools have been first published in the proceedings of the FPL conference series. Its objective is to bring together researchers and industry from all over the world for a wide ranging discussion of FPGAs, including, but not limited to: applications, advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, dynamic reconfiguration, etc.

 

Monday, August 31
8:30-8:45 Opening
8:45-9:40 Keynote 1 - Jason Cong: Customizable Domain-Specific Computing
9:45-11:15 Threads, MPI, Multi-CPU Systems Applications from the Practice Acceleration
  Session chair: TBD Session chair: TBD Session chair: TBD
9:45 M1A1 M1B1 M1C1
  MuCCRA-Cube: a 3D Dynamically Reconfigurable Processor with Inductive-Coupling Link
Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda and Hideharu Amano		 A Biophysically Accurate Floating Point Somatic Neuroprocessor
Yiwei Zhang, José Nuñez-Yañez, Joe McGeehan, Edward Regan and Stephen Kelly		 Compiler Assisted Runtime Task Scheduling on a Reconfigurable Computer
Mojtaba Sabeghi, Vlad-Mihai Sima and Koen Bertels
10:15 M1A2 M1B2 M1C2
  Hardware Implementation of MPI Barrier on an FPGA Cluster
Shanyuan Gao, Andrew Schmidt and Ron Sass		 An FPGA-based Transverse Multibunch Feedback System for Diamond Light Source
Isa S. Uzun, Mark T. Heron, Alun F. D. Morgan and Guenther Rehm		 Data Parallel FPGA Workloads: Software Versus Hardware
Peter Yiannacouras, J. Gregory Steffan and Jonathan Rose
10:45 M1A3 M1B3 M1C3
  Fast Critical Sections via Thread Scheduling for FPGA-based Multithreaded Processors
Martin Labrecque and J. Gregory Steffan		 CNP: An FPGA-based Processor for Convolutional Networks
Clément Farabet, Cyril Poulet, Yann LeCun and Jefferson Y. Han		 Generating High-Performance Custom Floating-Point Pipelines
Florent de Dinechin, Cristian Klein and Bogdan Pasca
   
11:15-11:45 Break & Poster Session 1
 
P1.1
Building Heterogeneous Reconfigurable Systems Using Threads
Jason Agron and David Andrews
P1.2
Reconfiguration-based Time-to-Digital Converter for Virtex FPGAs.
Ángel Quirós-Olozábal, Juan Manuel Barrientos-Villar and Mª de los Ángeles Cifredo-Chacón
P1.3
An Efficient Reconfigurable Architecture to Implement Dense Stereo Vision Algorithm Using High-Level Synthesis.
Mario Alberto Ibarra-Manzano, Michel Devy, Jean-Louis Boizard, Pierre Lacroix and Jean-Yves Fourniols
P1.4
High Speed Fixed Point Dividers for FPGAs
Gustavo Sutter and Jean-Pierre Deschamps
P1.5
A Self Reconfiguring Architecture to Support Multiple Fitness Functions in Genetic Algorithms
Charalampos Effraimidis, Kyprianos Papadimitriou, Apostolos Dollas and Ioannis Papaefstathiou
P1.6
Automatic Generation of FPGA Hardware Accelerators Using a Domain Specific Language
Ricardo Menotti, João Cardoso, Marcio Fernandes and Eduardo Marques
P1.7
A Dynamically Reconfigurable Parallel Pixel Processsing System
Daniel Llamoccca, Marios Pattichis and Alonzo Vera
P1.8
An Approach to System-Wide Fault Tolerance for FPGAs
Jano Gebelein, Heiko Engel and Udo Kebschull
P1.9
A Multi-Layered XML Schema and Design Tool for Reusing and Integrating FPGA IP
Adam Arnesen, Nathaniel Rollins and Michael Wirthlin
P1.10
Modular Design of Streaming and Reactive Systems using High-Level Interface Abstraction
Christopher Neely, Gordon Brebner and Weijia Shang
P1.11
Bitstream Compression Through Frame Removal and Partial Reconfiguration
Benjamin Sellers, Jonathan Heiner, Michael Wirthlin and Jeff Kalb
P1.12
Operation Scheduling for FPGA-based Reconfigurable Computers
Colin Yu Lin, Ngai Wong and Hayden Kwok-Hay So
P1.13
FPGA-Accelerated Retinal Vessel-Tree Extraction
Alejandro Nieto, Victor Brea and David López Vilariño
P1.14
Novel Strategies for Hardware Acceleration of Frequent Itemset Mining with the Apriori Algorithm
David W. Thöni and Alfred Strey
P1.15
A GPU-Inspired Soft Processor for High-Throughput Acceleration
Jeffrey Kingyens and J. Gregory Steffan
   
11:50-12:50 Keynote 2 - Peter Athanas: In Search of Agile Hardware
12:55-13:55 LUNCH
14:00-15:30 GPU, CPU, FPGA Register Allocation Partial Runtime Reconfiguration Synthesis, Low Power
  Session chair: TBD Session chair: TBD Session chair: TBD
14:00 M2A1 M2B1 M2C1
  Performance Comparison of Single-Precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core Processors
Nachiket Kapre and Andre DeHon		 A Runtime Relocation Based Workflow for Self Dynamic Reconfigurable Systems Design
Marco Domenico Santambrogio, Massimo Morandi, Marco Novati and Donatella Sciuto		 Improving Logic Density Through Synthesis-Inspired Architecture
Jason Anderson and Qiang Wang
14:30 M2A2 M2B2 M2C2
  Exploring Reconfigurable Architectures for Explicit Finite Difference Option Pricing Models
Qiwei Jin, David Thomas and Wayne Luk		 An Integrated Tool Flow to Realize Runtime-Reconfigurable Applications on a New Class of Partial Multi-Context FPGAs
Markus Rullmann, Renate Merker, Heiko Hinkelmann, Peter Zipf and Manfred Glesner		 Clock Gating Architectures for FPGA Power Reduction
Safeen Huda, Muntasir Mallick and Jason Anderson
15:00 M2A3 M2B3 M2C3
  Towards a Viable Out-of-order Soft Core: Copy-Free, Checkpointed Register Renaming
Kaveh Aasaraai and Andreas Moshovos		 FPGA Partial Reconfiguration via Configuration Scrubbing
Jonathan Heiner, Benjamin Sellers, Michael Wirthlin and Jeff Kalb		 Program-Driven Fine-Grained Power Management for the Reconfigurable Mesh
Heiner Giefers and Marco Platzner
   
15:30-16:00 Break & Poster Session 2
 
P2.1
Dynamic Polymorphic Reconfiguration for Anti-Tamper Circuits
Roy Porter, Samuel Stone, Yong Kim, J. Todd McDonald and LaVern Starman
P2.2
Run-time Partial Reconfiguration Speed Investigation and Architectural Design Space Exploration
Ming Liu, Wolfgang Kuehn, Zhonghai Lu and Axel Jantsch
P2.3
Dynamic Reconfigurable Mixed-Signal Architecture for Safety Critical Applications
Romuald Girardey, Michael Hübner and Jürgen Becker
P2.4
Using 3D Integration Technology to Realize Multi-Context FPGAs
Alessandro Cevrero, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici and Paolo Ienne
P2.5
MEMS Optically Reconfigurable Gate Array
Hironobu Morita and Minoru Watanabe
P2.6
SHARF: An FPGA-based Customizable Processor Architecture
Cem Savas Bassoy, Henning Manteuffel and Friedrich Mayer-Lindenberg
P2.7
Multigigabit Network Traffic Processing (Poster)
Ji?í Halák
P2.8
MACS: A Minimal Adaptive Routing Circuit-Switched Architecture for Scalable and Parametric NoCs
Rohit Kumar and Ann Gordon-Ross
P2.9
Fine Grain Partial Reconfiguration for Energy Saving in Dynamically Reconfigurable Processors
Toru Sano, Yoshiki Saito, Masaru Kato and Hideharu Amano
P2.10
A Low Cost Reconfigurable Soft Processor for Multimedia Applications: Design Synthesis and Programming Model
Sai Rahul Chalamalasetti, Wim Vanderbauwhede, Sohan Purohit and Martin Margala
   
16:00-17:30 GPU, CPU, FPGA and Image Processing Placement and Routing Applications #1
  Session chair: TBD Session chair: TBD Session chair: TBD
16:00 M3A1 M3B1 M3C1
  Performance Comparison of FPGA, GPU and CPU in Image Processing
Shuichi Asano and Tsutomu Maruyama		 An Analytical Model Relating FPGA Architecture and Place and Route Runtime
Scott Chin and Steve Wilton		 A Multi-FPGA Architecture for Stochastic Restricted Boltzmann Machines
Daniel L. Ly and Paul Chow
16:30 M3A2 M3B2 M3C2
  Self-Organizing Multi-cue Fusion for FPGA-based Embedded Imaging
Stefan Wildermann, Gregor Walla, Tobias Ziermann and Jürgen Teich		 RePlace: An Incremental Placement Algorithm for Field-Programmable Gate Arrays
Guy Lemieux and David Leong		 Comparing Fine-Grained Performance on the Ambric MPPA Against an FPGA
Brad Hutchings Brent Nelson
17:00 M3A3 M3B3 M3C3
  Optimizing the SUSAN Corner Detection Algorithm for a High Speed FPGA Implementation
Christopher Claus, Robert Huitl, Joachim Rausch and Walter Stechele		 Optimal Runtime Reconfiguration Strategies for Systolic Arrays
Arpith Jacob, Jeremy Buhler and Roger Chamberlain		 Low Power Techniques for Motion Estimation Hardware
Caglar Kalaycioglu, Onur Ulusel and Ilker Hamzaoglu
   
17:30-18:00 PhD Forum
 
PF1.1
High-level Programming of Coarse-grained Reconfigurable Architectures
Zain Ul-Abdin
PF1.2
FPGA Support for Satellite Computations of Hyper Spectral Images
Carlos González, Javier Resano and Daniel Mozos
PF1.3
Improving the Memory Footprint and Runtime Scalability of FPGA CAD Algorithms
Scott Chin and Steve Wilton
PF1.4
Efficient Techniques and Methodologies for Embedded System Design usign Free Hardware and Open Standards
Jose Ignacio Villar de Ossorno, Jorge Juan Chico and Manuel Jesus Bellido Diaz
PF1.5
Multi-Terminal BDD Synthesis and Applications
Petr Mikušek
PF1.6
Soft Errors in Flash-Based FPGAs: Analysis, Methodologies and First Results
Niccolò Battezzati, Filomena Decuzzi, Luca Sterpone and Massimo Violante
PF1.7
RISPP: A Run-Time Adaptive Reconfigurable Embedded Processor
Lars Bauer, Muhammad Shafique and Jörg Henkel
 
 
Tuesday, September 1
8:45-9:40 Keynote 3 - Jonathan Rose: The Evolution of Architecture Exploration of Programmable Devices
9:45-11:15 Fault Toleance and Reliability FPGA Architectures Surveys, Trends
  Session chair: TBD Session chair: TBD Session chair: TBD
9:45 T1A1 T1B1 T1C1
  Coarse-Grained Dynamically Reconfigurable Architecture with Flexible Reliability
Dawood Alnajjar, Younghun Ko, Takashi Imagawa, Hiroaki Konoura, Masayuki Hiromoto, Yukio Mitsuyama, Masanori Hashimoto, Hiroyuki Ochi and Takao Onoye		 Modeling Post-Techmapping and Post-Clustering FPGA Circuit Depth
Joydip Das, Steven Wilton, Philip Leong and Wayne Luk		 An ASIC Perspective on FPGA Optimizations
Andreas Ehliar and Dake Liu
10:15 T1A2 T1B2 T1C2
  A Novel SRAM-Based FPGA Architecture for Efficient TMR Fault Tolerance Support
Konstantinos Kyriakoulakos and Dionisios Pnevmatikatos		 Globally Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Systems
Masato Inagi, Yasuhiro Takashima and Yuichi Nakamura		 Recursion in Reconfigurable Computing: A Survey of Implementation Approaches
Iouliia Skliarova and Valery Sklyarov
10:45 T1A3 T1B3 T1C3
  Reconfigurable Fault Tolerance: A Framework for Environmentally Adaptive Fault Mitigation in Space
Adam Jacobs, Alan George and Grzegorz Cieslewski		   A Comparison of FPGA and FPAA Technologies for a Signal Processing Application
Roberto Selow
   
11:15-11:45 Break & Poster Session 3
 
P3.1
Rapid Design Exploration Framework for Applciation-Aware Customization of Soft Core Processors
Alok Prakash, Siew Kei Lam, Amit Singh and Thambipillai Srikanthan
P3.2
A Novel States Recovery Technique for the TMR Softcore Processor
Shiro Tanoue, Tomoyuki Ishida, Yoshihiro Ichinomiya, Motoki Amagasaki, Morihiro Kuga and Toshinori Sueyoshi
P3.3
Performance Metrics for Hybrid Computation in Multi-Tasking Systems
Kyle Rupnow, Jacob Adriaens, Wenyin Fu and Katherine Compton
P3.4
Cooperative Multithreading in Dynamically Reconfigurable Systems
Enno Luebbers and Marco Platzner
P3.5
The Educational Processor SWEET-16
Venelin Angelov and Volker Lindenstruth
P3.6
Secure FPGA Technologies and Techniques
An Braeken, Serge Kubera, Frederik Trouillez, abdellah Touhafi, Jo Vliegen and Nele Mentens
P3.7
FPGA Supercomputer Platforms: A Survey
Mariette Awad
P3.8
A Novel SEU, MBU and SHE Handling Strategy for Xilinx Virtex-4 FPGAs
Xabier Iturbe, Mikel Azkarate, Imanol Martinez, Jon Perez and Armando Astarloa
P3.9
Run-Time Resource Management in Fault-Tolerant Reconfigurable Network-on-Chip
Mohammad Hosseinabady and Jose Nunez-Yanez
P3.10
Hot-Swapping Architecture Extension for Mitigation of Permanent Functional Unit Faults
Zoltan Endre Rakosi, Masayuki Hiromoto, Hiroyuki Ochi and Yukihiro Nakamura
P3.11
SVM Speaker Verification System Based on a Low-Cost FPGA
Rafael Ramos-Lara, Mariano Lopez-Garcia, Enrique Canto-Navarro and Luis Puente-Rodriguez
P3.12
An FPGA-Based Embedded Wideband Audio CODEC System
Chang Choo, Bhavya Bambhania, Woon-Seob So, In-Ki Hwang and Do-Young Kim
   
11:50-12:50 Keynote 4 (Altera)
12:55-13:55 LUNCH
14:00-15:30 Arithmetic Interconnect (classical) Image Processing Applications
  Session chair: TBD Session chair: TBD Session chair: TBD
14:00 T2A1 T2B1 T2C1
  Noise Impact of Single-Event Upsets on an FPGA-based Digital Filter
Brian Pratt, Michael Wirthlin, Michael Caffrey, Paul Graham and Keith Morgan		 Area Estimation and Optimization of FPGA Routing Fabrics
Alastair M. Smith, George A. Constantinides and Peter Y. K. Cheung		 A Fast Parallel Matrix Multiplication Reconfigurable Unit Utilized in Face Recognition Systems
Ioannis Sotiropoulos and Ioannis Papaefstathiou
14:30 T2A2 T2B2 T2C2
  Exploiting Fast Carry-Chains of FPGAs for Designing Compressor Trees
Hadi Parandeh-Afshar, Philip Brisk and Paolo Ienne		 In Field Energy-Performance Tunable FPGA Architectures
Bita Nezamfar and Mark Horowitz		 Design Space exploration of Reconfigurable Systems for calculating Flying Object's Optimal Noise Reduction Paths
Dimitrios Kontos, Ioannis Papaefstathiou and Dionysios Pnevmatikatos
15:00 T2A3 T2B3 T2C3
  Large Multipliers with Less DSP Blocks
Florent de Dinechin and Bogdan Pasca		 Static versus Scheduled Interconnect in Coarse-Grained Reconfigurable Arrays
Brian Van Essen, Aaron Wood, Allan Carroll, Stephen Friedman, Robin Panda, Benjamin Ylvisaker, Carl Ebeling and Scott Hauck		 Real-Time Processing of Local Contrast Enhancement on FPGA
Kentaro Kokufuta and Tsutomu Maruyama
   
15:30-16:00 Break & Poster Session 4
 
P4.1
Off-Line Placement of Hardware Tasks on FPGA
Ikbel Belaid, Fabrice Muller and Maher Benjemaa
P4.2
PROTEUS: An Architectural Synthesis Tool Based on the Stream Programming Paradigm
Nikolaos Bellas, Sek Chai, Malcolm Dwyer, Dan Linzmeier and Abelardo Lagunas-Lopez
P4.3
Binary Synthesis with Multiple Memory Banks Targeting Array References
Yosi Ben-Asher and Nadav Rotem
P4.4
Mapping Basic Prefix Computations to Fast Carry-Chain Structures
Thomas Preußer and Rainer Spallek
P4.5
FPGA Implementation of Time-Multiplexed Multiple Constant Multiplication Based on Carry-Save Arithmetic
Roberto Gutierrez, Javier Valls and Asuncion Perez-Pascual
P4.6
Compensating for Variability in FPGAs by Re-Mapping and Re-Placement
Pete Sedcole, Edward Stott and Peter Cheung
P4.7
Synthesis of the SR Programming Language for Complex FPGAs
Nick Gasson and Neil Audsley
P4.8
Exploiting Synchronous Placement for Asynchronous Circuits onto Commercial FPGAs
Maurizio Tranchero
P4.9
FAST-Pricer: FPGA-based Accelerating Solution for Parallel Synthetic CDO Pricer
Joel Rossier, Carlos Pena, Joel Bovier and Dominik Madon
P4.10
Using C-to-Gates to Program Streaming Image Processing Kernels Efficiently on FPGAs.
Kristof Denolf, Stephen Neuendorffer and Kees Vissers
P4.11
An FPGA based Verification Platform for HyperTransport 3.x
Heiner Litz, Holger Froening, Maximilian Thuermer and Ulrich Bruening
P4.12
A Virus Scanning Engine Using a Parallel Finite-Input Memory Machine and MPUs
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura and Yoshifumi Kawamura
P4.13
Tracking Elephant Flows in Internet Backbone Traffic with an FPGA-based Cache
Martin Zadnik, Marco Canini, Andrew Moore, David Miller and Wei Li
P4.14
Implementation Issues on FPGA-Based Embedded Systems for Network Intrusion Detection
Dan Lo
   
16:00-17:30 Methodologies Interconnect (NoC) Application Acceleration #1
  Session chair: TBD Session chair: TBD Session chair: TBD
16:00 T3A1 T3B1 T3C1
  Enhancements to FPGA Design Methodology Using Streaming
Franjo Plavec, Zvonko Vranesic and Stephen Brown		 sFPGA2 - A Scalable GALS FPGA Architecture and Design Methodology
Rizwan Syed, Xiaolei Chen, Yajun Ha and Bharadwaj Veeravalli		 Accelerating HMMER Search Using FPGA
Toyokazu Takagi and Tsutomu Maruyama
16:30 T3A2 T3B2 T3C2
  General Methodology for Mapping Iterarive Approximation Algorithms to Adaptive Dynamically Partially Reconfigurable Systems
Josef Angermeier, Abdulazim Amouri and Jürgen Teich		 STAR-WHEELS Network-on-Chip Featuring a Self-Adaptive Mixed Topology and a Synergy of a Circuit- and a Packet-Switching Communication Protocol
Diana Goehringer, Bin Liu, Michael Huebner and Juergen Becker		 An Accelerator for K-th Nearest Neighbor Thinning Based on the IMORC Infrastructure
Tobias Schumacher, Christian Plessl and Marco Platzner
17:00 T3A3 T3B3 T3C3
  Optimising Designs by Combining Model-based and Pattern-based Transformations
Qiang Liu, Tim Todman and Wayne Luk		 A New Deadlock-free Fault-tolerant Routing Algorithm for NoC Interconnections
Slavisa Jovanovic, Camel Tanougast, Serge Weber and Christophe Bobda		 Efficient Particle-Pair Filtering for Acceleration of Molecular Dynamics Simulation
Matt Chiu and Martin Herbordt
   
19:00 DINNER
 
 
Wednesday, September 2
9:00-10:00 Keynote 5 (Xilinx)
10:00-11:30 Applications #2 Cryptography, Networking Watermarking, Chip ID
  Session chair: TBD Session chair: TBD Session chair: TBD
10:00 W1A1 W1B1 W1C1
  Implementation of a Reconfigurable Fast Fourier Transform Application to Digital Terrestrial Television Broadcasting
Florent Camarda, Jean-Christophe Prévotet and Fabienne Nouvel		 Pipeline Implementation of the 128-Bit Block Cipher CLEFIA in FPGA
Tomasz Kryjak and Marek Gorgon		 Increasing Stability and Distinguishability of the Digital Fingerprint in FPGAs through Input Word Analysis
Hiren Patel, Yong Kim, Jeffrey McDonald and LaVern Starman
10:30 W1A2 W1B2 W1C2
  IP Protection in Partially Reconfigurable FPGAs
Krzysztof Kepa, Fearghal Morgan and Krzysztof Kosciuszkiewicz		 Clock Duplicity for High-Precision Timestamping in Gigabit Ethernet
Carles Nicolau, Dolors Sala and Enrique Canto		 Towards a unique FPGA-Based Identification Circuit Using Process Variations
Haile Yu, Philip Leong, Heiko Hinkelmann, Leandro Möller and Manfred Glesner
11:00 W1A3 W1B3 W1C3
  Design and Evaluation of an Energy-Efficient Dynamically Reconfigurable Architecture for Wireless Sensor Nodes
Heiko Hinkelmann, Peter Zipf and Manfred Glesner		 Side-Channel Resistance for Light-Weight Implementations of Cryptographic Algorithms on FPGAs
Rajesh Velegalati and Jens-Peter Kaps		  
   
11:30-12:00 Break & Poster Session 5
 
P5.1
A Reconfigurable FIR/FFT Unit for Wireless Telecommunication Systems
Maroun Ojail, Raphaël David, Stéphane Chevobbe and Didier Demigny
P5.2
Efficient AES S-boxes Implementation in Non-volatile FPGAs
Lubos Gaspar, Viktor Fischer, Milos Drutarovsky and Nathalie Bochard
P5.3
Modularizing Flux Limiter Functions for a Computational Fluid Dynamics Accelerator on FPGAs
Kenta Inakagata, Hirokazu Morishita, Yasunori Osana, Naoyuki Fujita and Hideharu Amano
P5.4
Compact Architecture FPGA Implementation of Camellia
Panasayya yalla and Jens-Peter kaps
P5.5
FPGA-Based Acceleration of Neural Network for Ranking in Web Search Engine with a Streaming Architecture
Jing YAN, Ning-Yi XU, Xiong-Fei CAI, Rui GAO, Yu WANG, Rong LUO and Feng-Hsiung Hsu
P5.6
An FPGA Design for Evaluating Score Function in Protein Energy Calculation
Jose Manuel Romero-Ximil and Arturo Díaz-Pérez
P5.7
Emulating Spiking Neural Networks for Edge Detection on FPGA Hardware
Brendan Glackin, Jim Harkin, Thomas M. McGinnity, Liam P. Maguire and Qingxiang Wu
P5.8
A Reconfigurable Architecture for the Phylogenetic Likelihood Function
Nikolaos Alachiotis, Alexandros Stamatakis, Euripides Sotiriades and Apostolos Dollas
P5.9
Configuring Area and Performance: Empirical Evaluation on an FPGA-based Biochemical Simulator
Tomonori Ooya, Hideki Yamada, Tomoya Ishimori, Yasunori Osana, Yuichiro Shibata, Kiyoshi Oguri, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi and Hideharu Amano
P5.10
A FPGA Based Coprocessor for Gene Finding Using Interpolated Markov Model (IMM)
Grigorios Chrysos, Euripides Sotiriades, Ioannis Papaefstathiou and Apostolos Dollas
P5.11
DSP Robust Architecture to Complex Motion Scenes
Guillermo Botella Juan, Antonio García Rios, Manuel Rodríguez Álvarez and M. Carmen Molina Prego
P5.12
Dynamic Reconfiguration System for Real-Time Video Processing
Saya Hiinaga, Yoshiki Yamaguchi and Tohru Kawabe
P5.13
Numerically Controlled Oscillators Using Linear Approximation
Hans-Joerg Pfleiderer and Stefan Lachowicz
P5.14
Random Numbers Generation: Investigation of narrow transitions suppression on FPGA
Vladimir Rozic and Ingrid Verbauwhede
P5.15
Improving the Quality of a Physical Unclonable Function Using Configurable Ring Oscillators
Abhranil Maiti and Patrick Schaumont
P5.16
CREMA: A Coarse-grain REconfigurable Array with Mapping Adaptiveness
Fabio Garzia, Waqar Hussain and Jari Nurmi
   
12:00-13:00 Application Acceleration #2 Acceleration of Video Applications Application Acceleration #3
  Session chair: TBD Session chair: TBD Session chair: TBD
12:00 W2A1 W2B1 W2C1
  FPGA Accelerating Three QR Decomposition Algorithms in the Unified Pipelined Framework
Yong Dou, Jie Zhou, Xiaoyang Chen, Yuanwu Lei and Jinbo Xu		 A Toolset for the Analysis and Optimization of Motion Estimation Algorithms and Processors
Trevor Spiteri, George Vafiadis and Jose Luis Nunez-Yanez		 A Radix-8 Complex Divider for FPGA Implementations
Dong Wang, Milos D. Ercegovac and Nanning Zheng
12:30 W2A2 W2B2 W2C2
  FPGA-Accelerated Information Retrieval: High-Efficiency Document Filtering
Wim Vanderbauwhede, Leif Azzopardi and Mahmoud Moadeli		 Acceleration of Complex Algorithms on a Fast Reconfigurable Embedded System on Spartan-3
Enrique Cantó, Mariano Fons, Mariano López and Rafael Ramos		 A Highly Scalable Restricted Boltzmann Machine FPGA Implementation
Sang Kyun Kim, Lawrence McAfee, Peter McMahon and Kunle Olukotun
   
13:00-13:10 Closing
13:10-14:10 LUNCH

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