Euromicro Conference on Digital System Design (DSD 2009) - Patras, Greece

The Euromicro Conference on Digital System Design (DSD) addresses all aspects of (embedded and high-perfomance) digital and mixed hardware/software system engineering, down to microarchitectures, digital circuits and VLSI techniques. It is a discussion forum for researchers and engineers working on state-of-the-art investigations, development and applications.

It focuses on advanced circuit and system design and design automation concepts, paradigms, methods and tools, as well as on modern implementation technologies from full custom in nanometer technology nodes to FPGA and to multicore infrastructures. Compiler assisted ASIP, CMP, SMP, SMT, DSP-VLIW, GPU and platform based system design research results are welcome. Design and Verification Languages and Standards, Modeling, High Level Synthesis, Productive Design Technology and Engineering Flows, Efficiency, Density, Signal Integrity, Testability, Timing Analysis and Timing Closure, Power Consumption, Computational Power Speed and Performance, Manufacturability, Cost, Reliability, Error Resilience, Complexity, or Process Variability issues are covered in DSD.

KeynotesKeynote DSD 1 :
TransMutations: Towards a Human-quality Optimizing Compiler
by Prof. Alex Nicolau, Computer Science Dept., University of California, Irvine, USA

Keynote DSD 2:
Enabling the Next Major Step in Migrating Hardware Designs to Software
by Dr. Jeroen Leijten, Co-Founder and Chief Technology Officer of Silicon Hive, Eindhoven, The Netherlands.

Keynote DSD 3:
A Revolution in the Semiconductor Industry? The Shift of Innovation to the Edges
by Dr. Juan-Antonio Carballo, IBM Microelectronics Services, San Francisco, USA.

DATE: THURSDAY, 27/AUG/2009

9:00am

-

9:30am

OPEN: Opening

9:30am

-

10:30am

KN-1: Keynote 1 - DSD 1

TransMutations: Towards a Human-Quality Optimizing Compiler

Alex Nicolau

University of California, Irvine, United States of America

10:30am

-

11:00am

CB1: Coffee Break

11:00am

-

12:30pm

MPSoC-1: Systems-on-a-Chip and MultiProcessor SoCs (1)

A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC

Hajer Chtioui1,2,3, Rabie Ben Atitallah2,3, Smail Niar2,3, Jean-Luc Dekeyser2,4, Mohamed Abid1

1CES Laboratory, University of Sfax, Tunisia; 2Univ Lille Nord de France, Lille, France; 3UVHC, LAMIH, Valenciennes, France; 4INRIA, Villeneuve d'Ascq, France

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An Efficient Hardware Architecture for Packet Re-sequencing in Network Processors MPSoCs

Shadi Traboulsi1, Michael Meitinger2, Rainer Ohlendorf2, Andreas Herkersdorf2

1Ruhr Universität Bochum, Germany; 2Technische Universität München, Germany

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An Effective Replacement Strategy of Cache Memory for an SMT Processor

Yoshiyasu Ogasawara, Hironori Nakajo

Tokyo University of Agriculture and Technology, Japan

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An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload

Pierfrancesco Foglia1, Francesco Panicucci2, Cosimo Antonio Prete1, Marco Solinas1

1Università di Pisa, Italy; 2IMT Institute for Advanced Studies, Lucca, Italy

11:00am

-

12:30pm

SS-1: System Synthesis (1)

A Priority-Based Budget Scheduler with Conservative Dataflow Model

Marcel Steine1, Marco Bekooij2, Maarten Wiggers1

1Eindhoven University of Technology, The Netherlands; 2NXP Semiconductors, Eindhoven, The Netherlands

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Improving the Performance of the Divide-Add Fused Operation Using Variable Latency Quotient Generation

Alexandru Amaricai, Oana Boncalo

University Politehnica of Timisoara, Romania

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Distributed Collaborative Design of a Mixed-Signal IP Component

Adam Pawlak1, Piotr Penkala1,2, Pawe? Fra?1, Wojciech Sakowski1,2, Guenter Grau3, Szymon Grzybek2, Alexander Stanitzki3

1Silesian University of Technology, Gliwice, Poland; 2Evatronix, Gliwice, Poland; 3advICo GmbH, Recklinghausen, Germany

11:00am

-

12:30pm

CD-1: Circuit Design (1)

A Hazard-Free Delay-Insensitive 4-phase On-Chip Link Using MVCM Signaling

Mohammad Fattah, Soodeh Aghli Moghaddam, Siamak Mohammadi

University Of Tehran, Iran

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Improving Latency of Quantum Circuits by Gate Exchanging

Naser Mohammadzadeh, Morteza Saheb Zamani, Mehdi Sedighi

Amirkabir University of Technology, Iran

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Run-Time Reconfigurable Array using Magnetic RAM

Victor Silva1, Luís B. Oliveira2, Jorge R. Fernandes1, Mário P. Véstias3, Horácio C. Neto1

1INESC-ID / IST / UTL, Lisbon, Portugal; 2INESC-ID / FCT / UNL, Lisbon, Portugal; 3INESC-ID / ISEL / IPL, Lisbon, Portugal

11:00am

-

12:30pm

FTD-1: Fault Tolerance in Digital System Design (1)

Robustness Check for Multiple Faults using Formal Techniques

Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler

University of Bremen, Germany

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Instruction Precomputation for Fault Detection

Demid Borodin1, B.H.H. Juurlink1, Stefanos Kaxiras2

1Delft University of Technology, The Netherlands; 2University of Patras, Greece

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Soft Error Tolerant Asynchronous Circuits based on Dual Redundant Four State Logic

Werner Friesenbichler, Andreas Steininger

Vienna University of Technology, Austria

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High Availability Fault Tolerant Architectures Implemented into FPGAs

Martin Straka, Zdenek Kotasek

Brno University of Technology, Czech Republic

12:30pm

-

1:30pm

LB1: Lunch Break (Thursday)

1:30pm

-

2:30pm

KN-2: Keynote 2 - SEAA 1

2:30pm

-

4:00pm

MPSoC-2: Systems-on-a-Chip and MultiProcessor SoCs (2)

Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip

Maurizio Palesi, Fabrizio Fazzino, Giuseppe Ascia, Vincenzo Catania

DIIT, University of Catania, Italy

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Exploration of Slot Allocation for On-Chip TDM Virtual Circuits

Li Tong1, Zhonghai Lu2, Hua Zhang1

1Tianjin University of Technology, China; 2Royal Institute of Technology (KTH), Sweden

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Mapping Algorithms for NoC-based Heterogeneous MPSoC Platforms

Amit Kumar Singh, Wu Jigang, Alok Prakash, Thambipillai Srikanthan

Nanyang Technological University, Singapore

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Architectural Exploration of Per-Core DVFS for Energy-Constrained On-Chip Networks

Alexander Wei Yin, Liang Guang, Ethiopia Nigussie, Pasi Liljeberg, Jouni Isoaho, Hannu Tenhunen

University of Turku, Finland

2:30pm

-

4:00pm

SS-2: System Synthesis (2)

Power Management Aware Low Leakage Behavioural Synthesis

Sven Rosinger1, Kiril Schröder1, Wolfgang Nebel2

1OFFIS Institute for Information Technology, Germany; 2Carl von Ossietzky Universität Oldenburg, Germany

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Variation-Tolerant Design using Residue Number System

Ioannis Kouretas, Vassilis Paliouras

University of Patras, Greece

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Optimized Reconfigurable RTL Components for Performance Improvements During High-Level Synthesis

George Economakos, Sotiris Xydis

National Technical University of Athens, Greece

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Combined SD-RNS Constant Multiplication

Evangelos Vassalos, Dimitris Bakalis

University of Patras, Greece

2:30pm

-

4:00pm

CD-2: Circuit Design (2)

Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures

Ayse K. Coskun, Andrew B. Kahng, Tajana Simunic Rosing

University of California, San Diego, United States of America

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Calibration Method for a CMOS 0.06mm2 150MS/s 8-bit ADC

Nikos Petrellis, Michael Birbas, John Kikidis, Alexios Birbas

Analogies SA, Patras, Greece

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Bootstrapped Adiabatic Complementary Pass–Transistor Logic Driver Circuit for Large Capacitive Load and Low–Energy Applications

José-Carlos García1, Juan A. Montiel-Nelson1, Saeid Nooshabadi2, J. Sosa1, Héctor Navarro1

1University of Las Palmas de Gran Canaria, Spain; 2Gwangju Institute of Science and Technology, Gwangju, Republic of Korea

2:30pm

-

4:00pm

PI-1: Poster Introduction / Poster Session (1)

An Adaptive Unicast/Multicast Routing Algorithm for MPSoCs

Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberj, Hannu Tenhunen

University of Turku, Finland

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Model-Driven Design of Embedded Multimedia Applications on SoCs

Adolf Abdallah, Abdoulaye Gamatié, Jean-Luc Dekeyser

LIFL-USTL/CNRS, INRIA Lille Nord Europe, France

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GridRT: A Massively Parallel Architecture for Ray-Tracing using Uniform Grids

Alexandre Solon Nery1, Nadia Nedjah2, Felipe M.G. França1

1Universidade Federal do Rio de Janeiro, Brazil; 2Universidade do Estado do Rio de Janeiro, Brazil

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Using Integer Linear Programming in Test-Bench Generation for Evaluating Communication Processors

Eric Senn, David Monnereau, André Rossi, Nathalie Julien

Université de Bretagne Sud, France

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Reliability Estimation Process

Tobias Koal, Daniel Scheit, Heinrich T. Vierhaus

BTU Cottbus, Germany

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Time-Varying Network Fault Model for the Design of Dependable Networked Embedded Systems

Franco Fummi, Davide Quaglia, Francesco Stefanni

University of Verona, Italy

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Block-Level Fault Model-Free Debug and Diagnosis in Digital Systems

Raimund Johannes Ubar, Sergei Kostin, Jaan Raik

Tallinn University of Technology, Estonia

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High Performance Image Processing on a Massively Parallel Processor Array

Roberto R. Osorio, Cesar Díaz-Resco, Javier D. Bruguera

University of Santiago de Compostela, Spain

4:00pm

-

4:30pm

CB2: Coffee Break / Poster Session TH P1

4:30pm

-

6:00pm

MPSoC-3: Systems-on-a-Chip and MultiProcessor SoCs (3)

Thermal-Aware Test Scheduling for Core-based SoC in an Abort-on-First-Fail Test Environment

Zhiyuan He, Zebo Peng, Petru Eles

Linköping University, Sweden

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Low Power Encoding in NoCs based on Coupling Transition Avoidance

Meysam Taassori, Shaahin Hessabi

Sharif University of Technology, Iran

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Hierarchical NoCs for Optimized Access to Shared Memory and IO Resources

Andreas Lankes, Thomas Wild, Andreas Herkersdorf

Technische Universität München, Germany

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Storage Architecture for A On-chip Multi-core Processor

Mengxiao Liu, Weixing Ji, Jiaxin Li, Xing Pu

Beijing Institute of Technology, China

4:30pm

-

6:00pm

SAC: Synthesis of Arithmetic Circuits

Double-Precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs

Rui Duarte1, Horácio C. Neto1, Mário P. Véstias2

1INESC-ID/IST/UTL, Lisbon, Portugal; 2INESC-ID/ISEL/IPL, Lisbon, Portugal

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A Comparative Study of Parallel Prefix Adders in FPGA Implementation of EAC

Liu Feng1, Fariborz Fereydouni_Forouzandeh2, Otmane Ait Mohamed2, Gang Chen3, Xiaoyu Song4, Qingping Tan1

1National Lab of Parallel Distributed Processing, Hunan, China; 2ECE Department, Concordia University, Montreal, Quebec, Canada; 3Lingcore Lab, Portland, OR, USA; 4ECE department, Portland State University, Portland, OR, USA

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Streaming Reduction Circuit

Marco Gerards, Jan Kuper, André Kokkeler, Bert Molenkamp

University of Twente, The Netherlands

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Variable Latency Rounding for Golschmidt Algorithm with Parallel Remainder Estimation

Daniel Piso Fernández, Javier Díaz Bruguera

University of Santiago de Compostela, Spain

4:30pm

-

6:00pm

CD-3: Circuit Design (3)

Pulse Generation for On-chip Data Transmission

Simon J. Hollis

Department of Computer Science, University of Bristol, UK

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High Performance Bootstrapped CMOS Dual Supply Level Shifter for 0.5V Input and 1V Output

José-Carlos García1, Juan A. Montiel-Nelson1, Saeid Nooshabadi2

1University of Las Palmas de Gran Canaria, Spain; 2Gwangju Institute of Science and Technology, Gwangju, Republic of Korea

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Performance-Effective Compaction of Standard-Cell Libraries for Digital Design

Andrea Ricci, Ilaria De Munari, Paolo Ciampolini

Department of Information Engineering, University of Parma, Italy

4:30pm

-

6:00pm

FTD-2: Fault Tolerance in Digital System Design (2)

On the Risk of Fault Coupling over the Chip Substrate

Peter Tummeltshammer, Andreas Steininger

Vienna University of Technology, Austria

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Heterogeneous Multiprocessor Synthesis under Performance and Reliability Constraints

Makoto Sugihara

Toyohashi University of Technology, Japan

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A Hardware-Scheduler for Fault Detecion in RTOS-Based Embedded Systems

Jimmy Tarrillo, Leticia Bolzani, Fabian Vargas

Catholic University - PUCRS, Brazil

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Reliable Railway Station System based on Regular Structure implemented in FPGA

Jaroslav Borecký1,2, Pavel Kubalik1,2, Hana Kubátová1

1Czech Technical University in Prague, Czech Republic; 2IKT Advanced Technologies, Prague, Czech Republic

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Dependable Controller Design using Polymorphic Counters

Richard Ruzicka

Brno University of Technology, Czech Republic

Date: Friday, 28/Aug/2009
9:00am

- 10:00am
KN-3: Keynote 3 - SEAA 2

10:00am - 10:30am
CB3: Coffee Break / Poster Session FR P2

10:30am

-

12:00pm
MPSoC-4: Systems-on-a-Chip and MultiProcessor SoCs (4)

Internet-Router Buffered Crossbars Based on Networks on Chip

Kees Goossens1,2, Lotfi Mhamdi2, Iria Varela Senin2

1NXP Semiconductors, The Netherlands; 2Delft University of Technology, The Netherlands

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Network-on-Chip Architecture Exploration Framework

Timo Schönwald1, Jochen Zimmermann1, Oliver Bringmann1, Wolfgang Rosenstiel1,2

1FZI Forschungszentrum Informatik, Karlsruhe, Germany; 2Universität Tübingen, Germany

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Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor System-on-Chip

Giovanni Mariani1, Gianluca Palermo2, Cristina Silvano2, Vittorio Zaccaria2

1Università della Svizzera Italiana, Switzerland; 2Politecnico di Milano, Italy

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Approximate-Timed Transactional Level Modeling for MPSoC Exploration: a Network-on-Chip Case Study

Alexandre Guerre1, Nicolas Ventroux1, Raphäel David1, Alain Merigot2

1CEA, LIST, France; 2IEF, Université Paris Sud, Orsay, France

10:30am - 12:00pm

SLE: System-Level Energy Optimization of HW/SW Embedded Systems

A Standardized Knobs and Monitors RTL2RTL Insertion Methodology for Fine Grain SoC Tuning

Ahmed Mohamed AbdelHamid1,2, Ankur Anchlia1, Stylianos Mamagkakis1, Miguel Miranda Corbalan1, Bart Dierickx2, Maarten Kuijk2

1IMEC, Belgium; 2Vrije Universiteit Brussel , Belgium

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Conservative Dynamic Energy Management for Real-Time Dataflow Applications Mapped on Multiple Processors

Anca Molnos1, Kees Goossens1,2

1NXP Semiconductors, The Netherlands; 2Delft University of Technology, The Netherlands

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Compilation Technique for Loop Overhead Minimization

Nikolaos Kroupis1,2, Praveen Raghavan2,3, Murali Jayapala2, Francky Catthoor2,3, Dimitrios Soudris4

1Democritus University of Thrace, Greece; 2IMEC, Belgium; 3ESAT, KU Leuven, Belgium; 4ECE, NTUA Athens, Greece

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Pipelining-based High Throughput Low Energy Mapping on Network-on-Chip

Ming-Yan Yu, Ming Li, Jun-Jie Song, Fang-Fa Fu, Yu-Xin Bai

Micro-electronic Center, Harbin Institute of Technology, China

10:30am - 12:00pm

FDR-1: Flexible Digital Radio (1)

Open Platform for Prototyping of Advanced Software Defined Radio and Cognitiva Radio Techniques

Dominique Nussbaum1, Karim Kalfallah1, Raymond Knopp1, Christophe Moy2, Amor Nafkha2, Pierre Leray2, Julien Delorme2, Jacques Palicot2, Jerome Martin3, Fabien Clermidy3, Bertrand Mercier4, Renaud Pacalet5

1Eurecom, France; 2Supélec, Rennes, France; 3CEA LETI, Grenoble, France; 4Thales Communications, France; 5Institut Telecom, Paris, France

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Architecture and DSP Implementation of a DVB-S2 Baseband Demodulator

Panayiotis Savvopoulos, Nikolaos Papandreou, Theodore A. Antonakopoulos

University of Patras, Greece

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An Open and Reconfigurable Platform for 4G Telecommunication: Concepts and Application

Fabien Clermidy, Romain Lemaire, Xavier Popon, Dimitri Kténas, Yvain Thonnart

CEA LETI, Grenoble, France

10:30am - 12:00pm

FTDT: Fault Tolerance, Dependability and Testing

Deductive Fault Simulation for Asynchronous Sequential Circuits

Roland Dobai, Elena Gramatová

Institute of Informatics, Slovak Academy of Sciences, Slovakia

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ARROW ? A Generic Hardware Fault Injection Tool for NoCs

Michael Birner, Handl Thomas

Vienna University of Technology, Austria

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A Fault Tolerant NoC Architecture for Reliability Improvement and Latency Reduction

Amir Ehsani Zonouz, Mehrdad Seyrafi, Arghavan Asad, Mohsen Soryani, Mahmood Fathy, Reza Berangi

Iran University of Science and Technology, Iran

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Reliability Analysis of Qubit Data Movement for Distributed Quantum Computation

Oana Boncalo, Alexandru Amaricai

University Politehnica of Timisoara, Romania

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High Reliable Remote Terminal Unit for Space Applications

David Guzmán, Manuel Prieto, Daniel García, Victor Ruiz, Javier Almena, Sebastián Sánchez, Daniel Meziat

Universidad de Alcalá, Spain

12:00pm - 1:30pm
LB2: Lunch Break (Friday)

1:30pm - 2:30pm

KN-4: Keynote 4 - DSD 2

Enabling the Next Major Step in Migrating Hardware Designs to Software

Jeroen Leijten

Silicon Hive B.V., Eindhoven, The Netherlands

2:30pm - 4:00pm

PSS-1: Processor and System Synthesis (1)

SIMD Architectural Enhancements to Improve the Performance of the 2D Discrete Wavelet Transform

Asadollah Shahbahrami1,2, Ben Juurlink1

1Delft University of Technology, The Netherlands; 2University of Guilan, Rasht, Iran

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Simultaneous Multithreading VLIW DSP Architecture with Dynamic Dispatch Mechanism

Zheng Shen, Hu He, Yihe Sun

Tsinghua University, China

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Iterative Algorithm for Compound Instruction Selection with Register Coalescing

Minwook Ahn, Jonghee M. Youn, Youngkyu Choi, Doosan Cho, Yunheung Paek

Seoul National University, Republic of Korea

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CPLD-oriented Synthesis of Finite State Machines

Robert Czerwinski, Dariusz Kania

Silesian University of Technology, Poland

2:30pm - 4:00pm

SS-3: System Synthesis (3)

Architecture-Driven Synthesis of Reconfigurable Cells

Christophe Wolinski1, Krzysztof Kuchcinski2, Erwan Raffin3, François Charot1

1University of Rennes I / IRISA, France; 2Lund University, Sweden; 3Thomson R&D, Rennes, France

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An on Chip Network inside a FPGA for Run-Time Reconfigurable Low Latency Grid Communication

Jochen Strunk1, Toni Volkmer1, Wolfgang Rehm1, Heiko Schick2

1Chemnitz University of Technology, Germany; 2IBM Deutschland Research & Development GmbH, Germany

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Composable Resource Sharing Based on Latency-Rate Servers

Benny Akesson1, Andreas Hansson1, Kees Goossens2,3

1Eindhoven University of Technology, The Netherlands; 2NXP Semiconductors Research, The Netherlands; 3Delf University of Technology, The Netherlands

2:30pm - 4:00pm

FDR-2: Flexible Digital Radio (2)

A MPSoC Prototyping Platform for Flexible Radio Applications

Damien Hedde1, Pierre-Henri Horrein2, Frédéric Pétrot1, Robin Rolland3, Franck Rousseau4

1TIMA INPG/UJF/CNRS, Grenoble, France; 2CEA LETI, Grenoble, France; 3CIME-Nanotech, Grenoble, France; 4LIG, Grenoble, France

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Abstract Description of System Application and Hardware Architecture for Hardware/Software Code Generation

Amin EL MRABTI1, Hamed Sheibanyrad1, Frédéric Rousseau1, Frédéric Pétrot1, Romain Lemaire2, Jérôme Martin2

1TIMA Laboratory, France; 2CEA LETI, Minatec, Grenoble, France

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Reconfiguration Levels Analysis of FFT / FIR Units in Wireless Telecommunication Systems

Maroun Ojail1, Raphael David1, Stephane Chevobbe1, Didier Demigny2

1CEA, LIST, Embedded Computing Laboratory, France; 2LANNION/IRISA/CAIRN, France

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Flexible Architectures for LDPC Decoders based on Network On Chip Paradigm

Fabrizio Vacca1, Guido Masera1, Hazem Moussa2, Amer Baghdadi2, Michel Jezequel2

1Politecnico di Torino, Italy; 2TELECOM Bretagne, France

2:30pm - 4:00pm

PI-2: Poster Introduction / Poster Session (2)

High Performance CMOS 2-Input NAND Based on Low-Race Split-Level Charge-Recycling Pass-Transistor Logic

José-Carlos García1, Juan A. Montiel-Nelson1, Saeid Nooshabadi2

1University of Las Palmas de Gran Canaria, Spain; 2Department of Information and Communication, Gwangju Institute of Science and Technology (GIST), Republic of Korea

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Power Aware Fulfillment of Latency Requirements by Exploiting Heterogeneity in Wireless Sensor and Actuator Networks

Joris Borms1, Kris Steenhaut2, Bart Lemmens2, Ann Nowé1

1Vrije Universiteit Brussel, Belgium; 2Erasmus Hogeschool Brussel, Belgium

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The Case for a Balanced Decomposition Process

Petr Fišer, Jan Schmidt

Czech Technical University in Prague, Czech Republic

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Heuristic Synthesis of Multi-Terminal BDDs Based on Local Width/Cost Minimization

Petr Mikušek, Václav Dvo?ák

Brno University of Technology, Czech Republic

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Design, Simulation and Performance Evaluation of a NAND Based Single-Electron 2-4 Decoder

Nikos Konofaos1, George Alexiou2, Thomas Tsiolakis2

1University of the Aegean, Greece; 2University of Patras, Greece

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Adaptive Dynamic Voltage and Frequency Scaling Algorithm for Symmetric Multiprocessor Architecture

Marius Gligor, Nicolas Fournel, Frédéric Pétrot

TIMA Laboratory, Grenoble, France

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Survey of Test Data Compression Techniques Emphasizing Code Based Schemes

Usha Sandeep Mehta1, K. S. Dasgupta2, N. M. Devashrayee1

1Nirma University of Science and Technology, Ahmedabad, India; 2Space Application Center, ISRO, Ahmedabad, India.

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A Concept for Logic Self Repair

Tobias Koal, Daniel Scheit, Heinrich T. Vierhaus

BTU Cottbus, Germany

4:00pm - 4:30pm
CB4: Coffee Break / Poster Session FR P3

4:30pm - 6:00pm

PSS-2: Processor and System Synthesis (2)

A Synthesizable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor

Luis A. Tarazona, Douglas A. Edwards, Luis A. Plana

The University of Manchester, United Kingdom

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An Efficient Low-Complexity Alternative to the ROB for Out-of-Order Retirement of Instructions

Salvador Petit, Rafael Ubal, Julio Sahuquillo, Pedro López, Jose Duato

Universidad Politécnica de Valencia, Spain

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An Effective Methodology to Multi-Objective Design of Application Domain-Specific Embedded Architectures

Vincenzo Catania1, Alessandro G. Di Nuovo1, Maurizio Palesi1, Davide Patti1, Gianmarco De Francisci Morales2

1University of Catania, Italy; 2IMT - Institute for Advanced Studies, Lucca, Italy

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Energy and Performance Model of a SPARC Leon3 Processor

Sandro Penolazzi, Luca Bolognino, Ahmed Hemani

Royal Institute of Technology (KTH), Sweden

4:30pm - 6:00pm

RC-1: Programmable/Re-Configurable Architectures (1)

Acceleration of MELP Algorithm Using DSP Coprocessor with Extended Registers

Lu Gao, Li Guo, Canxing Lu

University of Science and Technology of China, China

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FPGA ACCELERATOR FOR RNA SECONDARY STRUCTURE PREDICTION

Arturo Díaz-Pérez1, Mario A. García-Martínez2

1Cinvestav-Tamaulipas, Mexico; 2Instituto Tecnológico de Orizaba, Mexico

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An FPGA-based Embedded System For Fingerprint Matching Using Phase-Only Correlation Algorithm

Giovanni Danese, Mauro Giachero, Francesco Leporati, Giulia Matrone, Nelson Nazzicari

University of Pavia, Italy

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xMAML: a Modeling Language for Dynamically Reconfigurable Architectures

Julien Lallet, Sebastien Pillement, Olivier Sentieys

IRISA-INRIA, Rennes, France

4:30pm - 6:00pm

APP-1: Applications of (embedded) digital systems (1)

A High Performance Hardware Architecture for One Bit Transform Based Motion Estimation

Abdulkadir Akin, Yigit Dogan, Ilker Hamzaoglu

Sabanci University, Turkey

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Memory Conflict Analysis and Interleaver Design for Parallel Turbo Decoding Supporting HSPA Evolution

Rizwan Asghar, Di Wu, Johan Eilert, Dake Liu

Linköping University, Sweden

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GPU Accelerated Solver of Time-Dependent Air Pollutant Transport Equations

Vaclav Simek, Radim Dvorak, Frantisek Zboril, Vladimir Drabek

Brno University of Technology, Czech Republic

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A Reconfigurable Frame Interpolation Hardware Architecture for High Definition Video

Ozgur Tasdizen, Ilker Hamzaoglu

Sabanci University, Turkey

4:30pm - 6:00pm

DTD: Dependability and Testing of Digital Systems

Transactions Sequence Tracking by means of Dynamic Binary Instrumentation of TLM Models

Antonio Da Silva1, Sebastián Sánchez2

1Universidad Politécnica de Madrid, Madrid, Spain; 2Universidad de Alcalá, Madrid, Spain

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Design of a Highly Dependable Beamforming Chip

Xiao Zhang, Hans G. Kerkhoff

Testable Design and Test of Integrated Systems Group, CTIT, University of Twente, The Netherlands

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One dimensional Systolic Inversion Architecture Based on Modified GF(2^k) Extended Euclidean Algorithm

Apostolos P. Fournaris, Odysseas Koufopavlou

University of Patras, Greece

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Signal Integrity and Power Integrity Methodology for Robust Analysis of On-the-Board System for High Speed Serial Links

Raj Kumar Nagpal1, Rakesh Malik1, Jai Narayan Tripathi2

1STMicroelectronics, Greater Noida, India; 2DA-IICT, Gandhinagar, India

Date: Saturday, 29/Aug/2009
9:00am

- 10:30am

LS: Logic Synthesis

Synthesizing Reversible Circuits for Irreversible Functions

D. Michael Miller1, Robert Wille2, Gerhard W. Dueck3

1University of Victoria, Canada; 2University of Bremen, Germany; 3University of New Brunswick, Canada

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A Fast SOP Minimizer for Logic Functions Described by Many Product Terms

Petr Fiser, David Toman

Czech Technical University in Prague, Czech Republic

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Representation of Incompletely Specified Index Generation Functions Using Minimal Number of Compound Variables

Tsutomu Sasao, Takaaki Nakamura, Munehiro Matsuura

Kyushu Institute of Technology, Iizuka, Japan

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Logic Minimization and Testability of 2SPP-P-Circuits

Anna Bernasconi1, Valentina Ciriani2, Gabriella Trucco2, Tiziano Villa3

1University of Pisa, Italy; 2University of Milano, Italy; 3University of Verona, Italy

9:00am

- 10:30am

RC-2: Programmable/Re-Configurable Architectures (2)

FPGA Implementations of SHA-3 Candidates: CubeHash, Grøstl, LANE, Shabal and Spectral Hash

Brian Baldwin, Andrew Byrne, Mark Hamilton, Neil Hanley, Robert P. McEvoy, Weibo Pan, William P. Marnane

University College Cork, Ireland

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Recursive Systematic Convolutional Code Simulation for OFDM - 802.11p System and FPGA Implementation Using an ESL Methodology

George C. Kiokes1, George Economakos2, Angelos Amditis1, Nikolaos K. Uzunoglu2

1Institute of Communication and Computer Systems, Athens, Greece; 2National Technical University of Athens, Greece

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Stereo Vision Algorithm Implementation in FPGA using Census Transform for Effective Resource Optimization.

Mario-Alberto Ibarra-Manzano1,2, Dora-Luz Almanza-Ojeda1,2, Michel Devy1,2, Jean-Louis Boizard1,2, Jean-Yves Fourniols1,2

1LAAS-CNRS, Toulouse, France; 2Université de Toulouse, Toulouse, France

9:00am

- 10:30am

APP-2: Applications of (embedded) digital systems (2)

The Parallel Sieve Method for a Virus Scanning Engine

Hiroki Nakahara1, Tsutomu Sasao1, Munehiro Matsuura1, Yoshifumi Kawamura2

1Kyushu Institute of Technology, Japan; 2Renesas Technology Corp., Japan

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Low-Power Low-Energy Prime-Field ECC Processor Based on Montgomery Modular Inverse Algorithm

Hamid Reza Ahmadi, Ali Afzali-Kusha

University of Tehran, Iran

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Methodology for Fast Pattern Matching by Deterministic Finite Automaton with Perfect Hashing

Jan Kaštil1, Jan Ko?enek1, Ond?ej Lengál2

1Brno University of Technology, Czech Republic; 2CESNET, Czech Republic

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An FPGA-based Embedded System for a Sailing Robot

Jose Carlos Alves, Nuno Alexandre Cruz

University of Porto, Portugal

9:00am

- 10:30am

WSN: Wireless Sensor Networks

Ad-hoc WSN in Biological Research

Perfecto Mariño, Fernando P. Fontán, Miguel Ángel Domínguez, Santiago Otero

University of Vigo, Spain

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Low Power Free Space Optical Communication in Wireless Sensor Networks

James Mathews, Matthew Barnes, D. K. Arvind

School Of Informatics, University of Edinburgh, United Kingdom

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A Framework for Compile- and Run-Time Management of Non-Functional Aspects in WSNs

Carlo Brandolese, William Fornaciari

Politecnico di Milano, Italy

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Remote Monitoring of Thermal Performance of Salinity Gradient Solar Ponds

Milan Nenad Simic, Randeep Singh, Louis Doukas, Aliakbar Akbarzadeh

RMIT University, Melbourne, Australia

10:30am - 11:00am
CB5: Coffee Break

11:00am - 12:00pm

KN-5: Keynote 5 - DSD 3

A Revolution in the Semiconductor Industry? The Shift of Innovation to the Edges

Juan-Antonio Carballo

IBM, San Francisco, United States of America

12:00pm - 12:30pm
CLOSE: Closing Session

12:30pm - 1:30pm
LB3: Lunch Break (Saturday)