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Power Implications of Implementing Logic Using FPGA Embedded Memory Blocks
September 10, 2008 - 4:03pm — scottcOn-chip user memory has become a common resource on modern FPGAs. This memory comes in the form of configurable Embedded Memory Blocks (EMB). EMBs are very area efficient for implementing designs
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FPL 2008 - Heidelberg, Germany
The International Conference
on Field Programmable Logic and Applications (FPL) is the first and
largest conference covering the rapidly growing area of
field-programmable logic. During the past 17 years, many of the
advances achieved in reconfigurable architectures, applications, design
methods and tools have been first published in the proceedings of the
FPL conference series.
Its
objective is to bring together researchers and industry from all over
the world for a wide ranging discussion of FPGAs, including, but not
limited to: applications, advanced electronic design automation (EDA),
novel system architectures, embedded processors, arithmetic, dynamic
reconfiguration, etc.
PROGRAM
| Monday, September 8, 2008 |
|||
| 08:00 | REGISTRATION | ||
| 08:30 |
OPENING |
||
| 08:45 |
KEYNOTE |
||
| 09:30 | BREAK | ||
| 10:00 |
PAPER SESSION 1 |
||
|
Modelling |
Encryption Applications | Network on Chip 1 | |
| 11:30 | BREAK & POSTER SESSION 1 |
||
| 12:00 | KEYNOTE | ||
| 12:45 | LUNCH | ||
| 14:00 | PAPER SESSION 2 | ||
| Analysis of Reconfigurability | Image and Video Processing | FPGA Architecture | |
| 15:30 | BREAK & POSTER SESSION 2 | ||
| 16:00 |
PAPER SESSION 3 |
||
| Dynamic Reconfiguration | Search and Matching Acceleration | Reconfigurable ASIP Design | |
| 17:30 | BREAK | ||
| 17:45 | PHD FORUM | ||
| 18:15 | WINE RECEPTION | ||
| 19:30 | CLOSE | ||
| Tuesday, September 9, 2008 |
|||
| 08:00 | REGISTRATION | ||
| 08:30 |
KEYNOTE |
||
| 09:15 | BREAK | ||
| 09:30 |
PAPER SESSION 4 |
||
|
Compiler for |
Novel Applications | Reconfigurable Processors | |
| 11:00 | BREAK & POSTER SESSION 3 |
||
| 11:30 | PAPER SESSION 5 | ||
| Analysis of Reconfigurability II | Random Number Generation & PLL | Networks on Chip II | |
| 13:00 | LUNCH | ||
| 14:00 | PAPER SESSION 6 |
||
| Codesign | FPGA Application in High Energy Physics |
Reconfigurable Processor Arrays | |
| 15:00 | TUTORIAL | ||
| 15:30 | BREAK | ||
| 16:00 |
PAPER SESSION 7 |
||
| Tools for FPGA Design | High Performance Computing for Financial and Biological Modelling | |
|
| 17:30 | BREAK & POSTER SESSION 4 | ||
| 18:00 | TRAM TO CASTLE | ||
| 19:00 | GALA DINER | ||
| 22:00 | CLOSE | ||
| Wednesday, September 10, 2008 |
|||
| 08:00 | REGISTRATION | ||
| 08:30 |
KEYNOTE |
||
| 09:15 | BREAK | ||
| 09:30 |
PAPER SESSION 8 |
||
|
Synthesis |
Algorithm Acceleration | Industrial Presentations |
|
| 11:00 | BREAK & POSTER SESSION 5 |
||
| 11:30 | PAPER SESSION 9 | ||
| Optimization | Surveys and Trends | ||
| 13:00 | CLOSING REMARKS | ||
| 13:15 | CLOSE | ||
FPGA Webcasts
Upcoming FPGA Events
- 2008 International Conference on ReConFigurable Computing and FPGAs (ReConFig'08) - Cancun, Mexico(Event or Conference)(1 day)
- SYSTEM VERILOG ASSERTIONS :: METHODOLOGY AND LANGUAGE TRAINING(Event or Conference)(2 days)
- SystemVerilog Assertions Language and Methodology Overview Seminar (Event or Conference)(14 days)
