World's 1st FPGA/CPLD Portal

FPGA-based prototyping is critical to ASIC verification and early software development. Many ASIC designs, however, are too large for a single FPGA and most verification teams lack a complete methodology for implementing such a design into a multi-FPGA prototyping system. Among the challenges that must be addressed are the implementation of complex clock structures and ASIC memories, the synthesis of non-FPGA friendly design constructs, and an efficient design partitioning to achieve a maximum system performance. In this practical seminar Mentor Graphics and ProDesign Electronics will outline a new approach to prototyping large ASIC designs and show how today's problems of implementing a large design into a multi-FPGA prototyping system will be solved.

Who Should Attend

> ASIC Designers
> Verification Engineers
> System Level Engineers

What You Will Learn

Agenda:

> Preparing your design
> Parallel module-based RTL synthesis
> Automatic design partitioning into multiple FPGAs
> Making incremental changes
> Extensive design verification and debugging methods