World's 1st FPGA Portal

Program:

8:15 - 9:00
Continental breakfast and registration

9:00 - 9:45
Session 1: Interconnect Trends and Standards
Jag Bolaria, senior analyst at The Linley Group, will present an overview of interconnect technology, standards, and silicon trends. These will include PCIe, RapidIO, HyperTransport, Display Interfaces, and Ethernet at 10Gbps and beyond.

9:45 - 12:00
Session 2: System Interconnects
This session will describe how leading system level interconnects such as PCIe and RapidIO can be used in different applications and what advantage each provides to the system designer.

PCI Express Gen-II Signal Conditioning and PC Graphics Switching Solutions
This presentation will discuss signal conditioning for PCI Express Gen-II, SAS and e-SATA interconnects for servers and PC Computing systems. The presentation will also cover high-speed switching between PC graphics and monitors/TVs based on PCI Express Gen-II and DisplayPort (DP) architectures.

In a World of Complex System-on-Chip Devices, are System Interconnects Still Needed?
External system-level interconnects are and have been key to constructing large systems out of relatively simple single-function devices. Recently, complex multicore System-on-Chip (SoC) devices have emerged with on-chip cross-bar fabrics interconnecting processor cores and accelerator functions. What impact does this trend have for external interconnects? Are some interconnects better able to leverage this trend than others? This presentation examines these questions as well as the trade-offs for selecting the optimum external interconnect.

RapidIO: The Embedded System Interconnect of Choice
Applications such as wireless base stations, video processing infrastructure, radar signal processing, military, and medical applications all require the use of multiple DSP and/or processors within a single system. Serial RapidIO is the optimal interconnect for processor communication in a true peer-to-peer environment, and allows inter-processor messaging with the low latency and high bandwidth that designers require, both chip-to-chip or across the backplane.

This presentation will review system architectures implemented with Serial RapidIO and discuss system interconnect scalability, flexibility, and software investment protection.

Designing 10Gbps Applications on Xilinx Virtex-5 Platforms
10Gbps applications are here today. OEMs are deploying systems to cater to the information explosion driven by convergence of voice, video, and data applications. Of primary importance is the choice of the data transport architectures to meet the stringent demands for bandwidth, latency and performance. This presentation will address scenarios and tradeoffs for designing with FPGAs using PCI Express, Serial RapidIO, XAUI, Ethernet, and other proprietary protocols. Also discussed will be key optimization and implementation strategies when designing the latest Xilinx Virtex-5 LXT/SXT/FXT platforms.

There will be a Q&A session after each talk.

12:00 - 1:00 Gourmet lunch, hosted speaker tables, and exhibits

1:00 - 2:40

Session 3: 10Gbps Ethernet and Beyond
This session will examine 10Gbps Ethernet PHY devices for optical and copper cabling. The session also looks at next generation technologies beyond 10GbE.

Migrating LANs from 1Gbps to 10Gbps
Teranetics will provide an overview of 10GBASE-T technology and show how it can enable substantial increases in LAN networking capabilities in the data center. We compare data handling capabilities of networking equipment based on 10GBASE-T with those of networking equipment based on 1000BASE-T in terms of throughput, density, cost per gigabit and other general metrics of interest.

Ethernet Backplane Connectivity on 10GBase-KR and Beyond for 100Gbps Systems
Aggregation requirements within the network and increased computing power in the data center are driving the need for 10Gbps ports. In modular systems, these 10Gbps ports need to be connected through a high-speed backplane. This presentation will focus on the issues and tradeoffs for building next-generation equipment where backplane connectivity needs to scale to 10GbE and beyond.

SFP+: The 10GbE Game Changer
This presentation will present a retrospect of the 10GbE optical market and explore future scenarios where the 10GbE market expands rapidly while simultaneously remaining nearly exclusively SFP+ based.

There will be a Q&A session after each talk.

3:00 - 3:45

Session 4: Choosing the Right Interconnect
This closing panel, moderated by Jag Bolaria, will focus on the relative strengths and positioning of leading interconnects. In addition to giving the audience an opportunity to ask questions, this session will address the changes expected in the leading interconnects. It will also look at the implementation challenges of using these interconnects.

Moderator: Jag Bolaria, The Linley Group
Panelists: Navneet Rao, Xilinx; Jose Tellado, Teranetics; Subhash Roy, AMCC;
additional panelists to be announced

3:45 - 4:45

Reception with Exhibits and Raffle.