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Cadence system level Techtorials - Chelmsford, MA
Achieving complete system verification and validation closure is among the most important challenges faced by designers and verification engineers today. The ability to run multiple engines in multiple levels of abstraction and verify hardware and software in parallel increases system quality and helps teams meeting schedules throughout the design and development process. The results include achieving first silicon working with first software.
This techtorial will cover the unique Cadence® solution to this challenge. Through lectures, industry speakers, and case studies, this techtorial will help you understand and leverage the latest products and flows that constitute a Cadence system-level verification methodology.
Key items detailed in this seminar include:
• Transaction-level modeling
• Transaction-based acceleration
• SystemC simulation
• In-circuit emulation
• Acceleration of constrained-random coverage-driven verification
• Hardware/Software co-verification
Agenda
9:30am –10:00am Registration/Breakfast
10:00am – 10:30am I ndustry challenges by keynote speaker
10:30am – 11:15am C adence high-speed simulation & advanced verification techniques
11:15am – 12:00pm Using coverage-driven verification to automate hardware/software co-verification
12:00pm – 12:30pm Hardware/software co-verification case studies
12:30pm – 1:30pm Lunch & special topic
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