How to Implement Communications and Signal Processing Algorithms in FPGAs and ASICs using Synplify DSP
Synplify DSP offers DSP hardware engineers and algorithm developers the most efficient way to get their algorithms into silicon for FPGAs and ASICs. Synplify DSP uses a unique DSP Synthesis technology that offers significant advantages over traditional design flows and competing DSP design tools. With a DSP modeling library that incorporates hardware abstraction and a powerful DSP synthesis engine, you can focus on algorithm behavior, eliminate the burden of hand coding architectural optimizations, and explore system-wide RTL area/speed optimizations automatically from a single algorithm model. This results in significantly faster time-to-market and achieves superior timing, area, and cost for DSP algorithm-based IC designs.
8:30 - 9:00am
Introduction to Synplicity
9:15 ÃƒÂ¢Ã¢â€šÂ¬Ã¢â‚¬Å“ 10:00
Introduction to Synplify DSP
This presentation introduces the concept of DSP synthesis and how it is different from other methods of going from a DSP algorithm specified in MATLAB/Simulink, to RTL code for hardware implementation. This discussion covers topics including design languages, the importance of a technology-independent flow, and automatic application of DSP synthesis optimizations.
10:00 - 10:15
10:15 ÃƒÂ¢Ã¢â€šÂ¬Ã¢â‚¬Å“ 11:30
Synplify DSP Product Demonstration
Several examples will be shown to illustrate how designs are captured in the Synplify DSP library and verified using MathworksÃƒÂ¢Ã¢â€šÂ¬Ã¢â€žÂ¢ Simulink. Design examples include a baseband processor for a QAM modem, a digital filter, and digital down conversion employing multirate signal processing. Once the Synplify DSP model is captured and verified in Simulink, it will be optimized and implemented into RTL using the Synplify DSP synthesis engine. Synplicity RTL synthesis tools will be used to target FPGAs from a single model or algorithm description without ever changing the source algorithm. The demonstration will also show how Synplify DSP can be used to re-target implementation in ASIC silicon.
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