World's 1st FPGA Portal

This one-day event covers the latest technology trends, tips, and traps in using and understanding the IP blocks available from leading vendors.

Lineup of technical presenters, including:

The Linley Group's Principal Analyst, Linley Gwennap, will provide a CPU and IP Overview

SafeNet's Systems Engineering Manager, Steve Singer, will present "How Application Requirements Drive Security Architecture"

IPextreme's CEO, Warren Savage, will present "Licensing Freescale’s Power Architecture and ColdFire Technologies"

Tensilica's Principal System Architect, Jerry Redington, will present "Networking Applications for Xtensa Configurable Processors"

MIPS' Director of Engineer, Vidya Rajagopalan, will present "Accelerating Networking Functions Using MIPS32"

ARM will present "Evaluating Multicore Tradeoffs for SMB Networking"

IBM will present "Building a Single-Chip Control/Data Plane"

T-RAM's Farid Nemati, CTO and Founder, will present "Thyristor-RAM: A Novel Embedded Memory Technology that Outperforms Embedded SRAM and DRAM"

The seminar is intended for designers of networking or communications ASICs or SoC products that use licensed intellectual property, including designers at equipment companies or semiconductor vendors. These designers will learn about the newest IP products as well as how to evaluate, integrate, configure, and program these IP cores for applications similar to the ones they are designing. Attendance is free to qualified attendees; others pay $495.