Prototyping as a Productive Verification Methodology - Austin, TX

Start: Jun 24 2008 - 8:45am

End: Jun 24 2008 - 2:30pm

Timezone: Etc/GMT-8

Where:

Embassy Suite Austin Arboretum, 9505 Stonelake Boulevard, Austin, TX

Event/Conference Information URL:

Click here to Register

Who should
attend?

ASIC and FPGA Engineers
System Architects
Engineering or Technical
Managers

FPGA-based Prototyping has
become a mandatory step for successful ASIC/ASSP and SoC design. The use of
FPGAs for ASIC or SoC design verification is no longer the "ad-hoc / assembly
required" methodology it once was; It has evolved into a truly productive and
high-performance ASIC verification solution.

What should you consider
when deploying an FPGA-based prototyping system? And, what are the necessary
steps involved in getting an ASIC design to work on an FPGA-based prototyping
board? You will learn this and more during this FREE technical and educational
seminar.

What You Will Get

A closer look at the
HAPS™ architecture and capabilities; System set-up and configuration; Getting
the most out of a prototyping system.
Live demonstrations of
the complete flow:
- Preparing the ASIC
  design for prototyping
- Designing partitioning
  and implementation
- Prototyping system
  configuration and bring-up
- Debugging the design
  and fixing errors

Agenda

9:00 – 9:15	Welcome and Introduction
9:15 – 9:45	Chip Design Magazine to Present: "Verification Market and Technology Trends"
9:45 – 11:00	Synplicity, Inc. to Present: "Prototyping - A Mandatory Step for Successful ASIC/ASSP and SoC Design"
11:00 – 11:15	Break
11:15 – 12:00pm	The HAPS Prototyping System: A closer look at the HAPS architecture and capabilities; system setup, challenges, and results.
12:00 – 1:00	Lunch, Demonstrations, Exhibits
1:00 – 2:00	Synplicity, Inc. to Present: "The Confirma™ Platform Demonstration"
2:00 – 2:30	Q&A and Prize draw