Logic NVM 2008 - Santa Clara, CA

Dr. Yoon Lee
Managing Director of Product Innovation Team (PIT)
Samsung Electronics’ Global Marketing Operation

Configuring Your NVM
The starting point for embedded non-volatile memory can be confusing
for a designer. Lots of questions seem to crop up. For example, what
exactly should you be embedding into that memory die, and what are the
tradeoffs that come with those decisions. Should you be thinking about
embedding the memory into the logic, or vice versa, and why? Should
your memory include a one-time programmable (OTP) section or should it
be "multiple-time" programmable? What are the strengths and weaknesses
of adding just a few bytes of memory, and what are the "must-have"
features? These are the questions that will be answered by this
esteemed panel, as well as any others that you are welcome to ask.

Moderator: Alan Niebel, Founder and CEO of Web-Feet Research.
Panel:

Todd Humes, Vice President of Engineering IP products, Impinj
Charles Ng, Vice-President of Worldwide Sales & Marketing,
Kilopass Technology
Joel Rosenberg, Senior Director of Digital Consumer Marketing,
Virage Logic
Xerxes Wania, CEO and President, Sidense

Applications Track – Room: San Thomas
Cryptographic Authentication Through RSA Digital Signature Algorithms
Speaker: Al Hawtin, Elliptic Semiconductor
Cryptographic authentication through RSA digital signature algorithms
are used both for secure boot and for anti-cloning technologies in SoC
designs. Secure boot ensures that the system loads only the code which
is factory authorized and prevents hackers from modifying the system
code in Flash and taking control of the product for malicious reasons.
Anti-cloning techniques use embedded secrets in the device to ensure
that only authorized systems will function correctly. The presentation
explains the cryptographic design used to achieve these features as
well as the NVM solutions best suited to the task of storing the
embedded secrets required for these two applications.

Integration Track – Room: Lawrence
Design Selection Alternatives for Integrated Memory
Speaker: Gregory A. Quirk, Product Manager, TechOnline
Logic NVM is one of many different alternatives for designers to
provide some memory capabilities without incorporating a separate
component, such as an EEPROM or DRAM. But why would you choose logic
NVM over another solution? How does it compare to popular choices like
embedded flash and fuse/antifuse technologies? The presentation will
provide an overview of these three solutions and provide comparison and
contrasts between them using technical in depth detailed analysis from
Semiconductor Insights. As well, an overview of the intellectual
property (IP) for logic NVM will be discussed and some of the more open
spaces for further development identified.

Applications Track – Room: San Thomas
Logic NVM for Precision Analog and Timing Circuits in CMOS
Speaker: Michael S. McCorquodale, Ph.D., Chief Technical Officer, Mobius Microsystems

The
use of high-resolution analog current, voltage and switched-capacitor
trimming has proven critical to the development of Mobius’
self-referenced CMOS oscillator technology for quartz crystal
replacement. Mobius’ components are the highest-accuracy all-CMOS
frequency references on the market. The use of logic NVM in Mobius’
timing products is discussed within the general context of storing
trimming and configuration coefficients for precision analog components.

Quality and Reliability Track – Room: Lawrence
Logic NVM Technologies: IP Qualification Requirements
and Methods
Speaker: Pearl Cheng, Vice President of Engineering and
Operations, Kilopass
There are three primary categories of non-volatile memory technology
developed on standard logic CMOS process technologies: fuse, anti-fuse,
and floating gate. The intrinsic nature of all of three of these
technologies is to either effect a physical, and, thereby, electrical
change in a semiconductor material or to store a charge within a
floating gate in order to store information. The storage mechanisms
involve effects on CMOS device materials that are not necessarily
intended by the wafer manufacturer. Although there is a substantial
investment required, it is critical that Logic NVM IP vendors qualify
their technologies in order to provide necessary quality and
reliability assurances, as well as protections to the end customer.
This presentation discusses the qualification requirements and methods
needed for the qualification of Logic NVM IP technologies as well as
the underlying benefit to the end customer provided with this
qualification information.

Quality and Reliability Track – Room: San Thomas
Reliability Characterization Challenges and Methodologies
for OTP Memory Arrays
Speaker: Wlodek Kurjanowicz, CTO, Sidense
Embedded one-time programmable (OTP) memory has been employed for
several years as an inexpensive and relatively easy-to-implement
storage mechanism. Traditional technologies such as ROM and eFuse have
been in widespread use, but limitations with regard to
field-programmability, long-term reliability and storage security have
prompted several vendors to investigate other OTP mechanisms for
implementing embedded data and code storage. This has led to the
introduction by several vendors of antifuse-based embedded OTP memory
IP, some using oxide breakdown as a way to program memory bits. This
tutorial reviews OTP qualification challenges and describes an
effective reliability test methodology used for memory arrays based on
a unique split-channel OTP bit cell. The tutorial will also include
associated silicon test results.

Testability Track – Room: Lawrence
Embedded Non-Volatile Memory with Efficient Testability
Speaker: TBD
An Embedded Non-Volatile multi-programmable solution has been developed
with several features that facilitate efficient testability. The Page
programming feature provides a very efficient method of storing many
bits in parallel thereby minimizing test time and cost. The Margin mode
provides a simple expedient method of monitoring the program margin for
all bits in the array. The Vt distribution test allows for the
measurement of programming threshold voltages for every individual bit
thereby facilitating efficient product qualification. The product has
been successfully developed in 130 nm and 90 nm technologies and
results will be shown.

Quality and Reliability Track – Room: Lawrence
Reliable Multi-time Programmable NVM on Advanced Process Nodes
Speaker: Dave Sowards, VP NVM Products, Virage Logic
Floating poly based NVM has been successfully implemented in a range of
pure logic processes from 180nm down to 90nm. In 90nm process and below
there is shift from 3.3V IO (70A oxide) to 2.5V IO (50A oxide). The
viability of a floating gate NVM implementation for thin oxide
manufactured on a standard CMOS process will be demonstrated. Specific
topics will include architecture, endurance cycling, retention and
device reliability.

Testability Track – Room: Lawrence
Production Test Methodology for Manufacturable NVM
Speaker: Martin Niset, Product and Test Engineering Manager, Impinj
The ideal production test flow guarantees that the device under test
meets all the datasheet specifications while keeping test time at a
minimum. Achieving such a feat with an NVM array presents many
challenges including: (1) validating the electrical performance across
temperature, (2) guaranteeing key end of life reliability metrics such
as data retention and (3) managing test time regardless of the array
size. This paper addresses test strategy and unique Design For Test
features required to meet those challenges.