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The IEEE/IFIP International Symposium on Rapid System Prototyping
(RSP) explores trends in Rapid Product Development of Computer Based
Systems. Its scope ranges from formal methods for the verification of
software and hardware systems to case studies of actual software and
hardware systems. It aims to bring together researchers from the
hardware and software communities to share their experiences and to
foster collaboration of new and innovative Science and
Technology.

Symposium Program

Tuesay the 3rd of June

8.30 – 9.00: Registration

9.00 – 9:30: Introduction

• Message from the General Chairs

  • M. Shing - NPS, USA

  • W. Hardt - Tech. Univ. Chemnitz,
    Germany

• Message from the Program Chairs

  • F. Hessel - PUCRS, Br

  • J. Hugues - TELECOM ParisTech, F

9.30 – 10:30: Keynote Speech by Greg Bollella

• The RTSJ for
  Prototyping Real-Time Systems: A Case Study

10.30 – 10.50: Coffee Break

10.50 – 12.20 Session 1: System Specification, Session
Chair: Fabiano Hessel, PUCRS, Brazil

• RealSpec: An Executable Specification Language for
  Prototyping Concurrent Systems
  A. Khwaja, J. Urban,
  Intel Corporation, USA
• Using MDE for the Rapid Prototyping of Space Critical
  Systems
  J. Hugues, M. Perrotin, T. Tsiodras, GET -
  Telecom Paris, France
• A Functional DIF for Rapid Prototyping
  W.
  Plishker, N. Sane, M. Kiemb, K. Anand, S. Bhattacharyya,
  University of Maryland, USA

12.20 – 13.40: Lunch

13.40 – 15.10 Session 2: Embedded Software Design, Session
Chair: Klaus Müller-Glaser - Univ. Karlsruhe (ITIV), Germany

• High-Level Estimation of Execution Time and Energy
  Consumption for Fast Homogeneous MPSoCs
  Prototyping
  S. Filho , J. C. Palma , C. Marcon ,
  F. Hessel, PUCRS, Brazil
• Software for Multi Processor System on Chip: moving
  from generic RISC platforms to CELL
  L. Demontes,
  M. Bonaciu, P. Amblard, University of Grenoble, France
• Multi-CPU/FPGA Platform Based Heterogeneous
  Multiprocessor prototyping: New Challenges for Embedded
  Software Designers
  B. Senouci , A.
  Kouadri-Mostéfaoui , F. Rousseau , F. Petrot, TIMA Laboratory,
  France

15.10 – 15.30: Coffee Break

15.30 – 17.00 Session 3: MPSoC Design, Session Chair:
George Alexiou - Univ. Patras/RA-CTI, Greece

• Configurable Heterogeneous MPSoC Architecture Exploration Using
  Abstraction Levels
  H. Shen, P. Gerin, F. Petrot,
  TIMA Laboratory, France
• An Automated Design Flow for NoC-based MPSoCs on FPGA
  S.
  Lukovic, L. Fiorin,
  ALaRI-Faculty of Informatics-University of Lugano, Suisse
• Integrating Abstract NoC Models within MPSoC
  Design
  E. Moreno, K. Popovici, N. Calazans,
  A. Jerraya, PUCRS, Brazil and CEA-LETI, France

17.00 – 18.00 Industrial Panel Session: New Frontiers in
Chip Design

• Moderator: F. Hessel (PUCRS, Brazil)
• Panelists: A. Donlin (Xilinx), F. Clermidy (CEA-LETI), G. Marin
  (Tensilica), A. Mathur (Calypto)

18.00 – 20.00 Welcome
Reception

Wednesday, 4th of June

9.00 – 10.00: Keynote Speech by Bruce Lewis

• Multi-Dimensional Model Based
  Engineering for Performance Critical Computer Systems Using
  AADL

10.00 – 10.30: Coffee Break

10.30 – 12.00 Session 4: Methodology, Session Chair:
Jérôme Hugues - ENST Paris, France)

• Automation of Communication Refinement and Hardware
  Synthesis within a System-Level Design
  Methodology
  L. Moss, M. Cantin, G. Bois ,
  M. Aboulhamid, École Polytechnique de Montréal and
  Université de Montréal, Canada
• A Methodology for Wireless Sensor Network Prototyping
  with Sophisticated Debugging Support
  H. Hinkelmann,
  A. Reinhardt, M. Glesner, Technische Universitaet Darmstadt,
  Germany
• Design Flow for Reconfiguration based on the
  Overlaying Concept
  A. Meisel, A. Draeger,
  S. Schneider, W. Hardt, Chemnitz University of Technology,
  Germany

12.00 – 13.30: Lunch

13.30 – 15.00: Session 5: Verification, Session Chair:
Doron Drusinsky - Naval Postgraduate School, USA

• A Coverage-Driven Constraint Random-Based Functional
  Verification Method of Memory Controller
  Y. Wu,
  L. Yu, L. Lan, H. Zhou, Beijing Microelectronics Technology
  Institute, China
• Requirement Traceability in Software Developmet
  Process: An Empirical Approach
  S. Bhattacharya ,
  S. Sengupta , A. Kanjilal, Jadavpur University, India
• Dynamic adaptation of Hardware-Software scheduling for
  Reconfigurable System-on-Chip
  F. Ghaffari,
  B. Miramond, F. Verdier, University of Cergy Pontoise,
  France

15.00 – 15.30: Coffee Break

15.30 – 17.30: Session 6: FPGA Design, Session Chair: Ahmed
Jerraya - CEA-LETI, France

• A Multi-MicroBlaze Based SOC System: From SystemC
  Modeling to FPGA Prototyping
  S. Xu,
  H. Pollitt-Smith, CMC Microsystems, Canada
• From Application to ASIP-based FPGA prototype: a Case
  Study on Turbo Decoding
  O. Muller, A. Baghdadi,
  M. Jézéquel, TELECOM Bretagne, France
• A prototype of trusted platform functionality on
  reconfigurable hardware for bitstream
  updates
  B. Glas, A. Klimm, D. Schwab,
  K. Müller-Glaser, Jürgen Becker, University of Karlsruhe
  (ITIV), Germany
• Co-Design Architecture and Implementation for
  Point-Based Rendering on FPGAs
  M. Majer,
  S. Wildermann, J. Angermeier, S. Hanke, J. Teich, University
  Erlangen-Nuremberg, Germany

20.00: Banquet

Thursday, 5th of June

9.00 – 10.00: Keynote Speech by Eric Sax

• Testing automotive
  system prototypes far before driving on the proving
  ground

10.00 – 10.30: Coffee Break

10.30 – 12.00 Session 7: Image Processing, Session Chair:
Wolfram Hardt - TU Chemnitz, Germany

• Implementation Strategies for Statistical Codec
  Designs in H.264/AVC Standard
  X.H. Tian, T. M. Le,
  X. Jiang and Y. Lian, National University of Singapore,
  Singapore
• ASIP-controlled Integer Transform Codec for H.264/AVC
  Coding
  N.T. Ngo, T.T.T. Do, Y.S. Kadam, T.M. Le and
  A. Bermak (*), National University of Singapore, Singapore,
  (*) Hong Kong University of Science and Technology, Hong
  Kong
• A Novel System-on-Chip Architecture for Efficient
  Image Processing
  V. Mariatos, K. D. Adaos,
  G.P. Alexiou, Diaplous Machine Vision, Greece

12.00 – 13.30: Lunch

13.30 – 15.30 Session 8: Case Studies, Session Chair:
Man-Tak Shing - Naval Postgraduate School, USA

• Application Specific Instruction Sets and their Impact
  on the Design Space Requirements of a Hardware Java Virtual
  Machine
  Ryan Wood , Joseph Libby , Kenneth Kent,
  University of New Brunswick, Canada
• Flexible Software-Hardware Network Intrusion Detection
  System
  Kenneth Kent , Eric Aubanel , Ryan Proudfoot
  , Nan Chen, University of New Brunswick,
  Canada
• MAJIC: Multi-Agent Java Interface
  Controller
  Greg Ball, Naval Postgraduate School,
  USA
• Bandwidth Requirement Determination for a Digitally
  Controlled Cavity Synchronisation in a Heavy Ion Synchrotron
  Using Ptolemy II
  Christopher Spies , Peter Zipf ,
  Manfred Glesner , Harald Klingbeil, Technische Universität
  Darmstadt, Germany

15.30 – 16.00

• Information about RSP’09
• Farewell