World's 1st FPGA/CPLD Portal

Mentor Graphics' inFact testbench automation solution is the first to use intelligent algorithms to synthesize meaningful testbench sequences while allowing the user to set verification goals prior to simulation and determine verification priorities.

Seating is VERY limited to maximize your learning experience, so submit your interest immediately to request your spot. Continental breakfast and lunch are provided.
Who Should Attend

* Verification engineers
* Verification managers

What You Will Learn

* How intelligent testbench automation tools can help you rapidly reach higher verification coverage
* How inFact's capabilities allow the creation of scalable, re-usable verification components
* How intelligent testbench components fit into your overall verification architecture
* How to construct an inFact intelligent testbench using step-by-step, hands-on exercises with a simple example